JPS58136157A - Data input circuit - Google Patents

Abstract

PURPOSE:To eliminate inputting an abnormal data due to the delay in data input, by constituting the titled circuit of two latch circuits and two logical product circuits. CONSTITUTION:A point designation signal from a CPU1 and a point strobe signal are inputted to a latch circuit 2 to designate a point to the circuit 2. Based on the latch output signal from the circuit 2, a logical product circuit 3 is opened and data are inputted to a latch circuit 5 through an input data bus e' from an input data bus (e) via the circuit 3. After the time when the data from the bus e' is transmitted to a circuit 5 is elapsed, a data latch signal (f) is outputted from the CPU1, a logical product circuit 4 is opened and the data is inputted to the CPU1 through a data bus e'''. Thus, the delay in the data input is produced in the timing of data input of the CPU1, allowing to eliminate an abnormal data input.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a data input circuit, and more particularly to a data input circuit that prevents data transmission delays due to the length of a signal cable.

FIG. 1 is a block diagram of a data human circuit that has been used conventionally. In other words, the point designation signal and point strobe signal from the CPU 1 are sent to the latch circuit 2.
and specify the point to latch circuit 2.

Next, the AND circuit 3 is opened based on the latch output signal from the latch circuit 2, and the input data bus C receives the data 1.
J - The signal is input to one input terminal of the AND circuit 4 at the next stage via the product circuit 3 and the input data bus C'. Next, a data input signal is output from the CPU 1 to open the AND circuit 4, and data is input to the CPU through the input data bus e''.

However, in the conventional data input circuit described above, the CPU
If the signal line connecting the AND circuit 4 is long, the data input will be delayed from the data input timing of the CPU due to data delay, resulting in incorrect data being input.

The present invention was made in response to the above circumstances, and an object of the present invention is to provide a data input circuit that prevents delays in data transmission.

Hereinafter, a data input circuit according to the present invention (hereinafter referred to as the circuit of the present invention) will be explained.

FIG. 2 is a block diagram of the circuit of the present invention.

In other words, a point designation signal and a point strobe signal from the CPU] are input to the latch circuit 2, and a point is designated to the latch circuit. Next, the AND circuit 3 is opened based on the latch output signal from the latch circuit 2, and the data is transferred from the input data bus C via the AND circuit 3 and through the input data bus C' to a separate latch circuit 5. Enter. Next, after a period of time for the data from the data bus C' to be transmitted to the latch circuit 5, a data latch signal f is sent from cpul.
is output and data e'' is latched.Next, a data input signal is output from the CPU 1, the AND circuit 4 is opened, and data is input to the CPU through the data bus C''.

Next, the operation of the data input circuit having the above configuration will be explained according to the timing chart of FIG.

First, based on the input of the point designation signal and the point strobe signal, the output of the latch circuit 2 becomes l'-L at the same time as the point strobe signal rises, as shown in Figure 3 (i/X).
The signal changes from OWJ to HIGHJ and is input to the AND circuit 3 as a latch output. The output from the AND circuit 3 is input to the second latch circuit 5, and based on the output and the data latch signal, the latch circuit 5 outputs an output as shown in FIG. The product circuit 4 is opened,
The data input signal from the CPU is sent to the CPU by the AND circuit 4 in a signal waveform as shown in FIG. 3 (H).

To summarize, the present invention includes: a first latch circuit that outputs a latch output based on a point designation signal and a point strobe signal output from the CPU; a first AND circuit that outputs, the first AND circuit and the CP;
Based on the data latch signal from the CPU, a second latch circuit is input to the second AND circuit and the output of the second latch circuit is opened, and the data input from the CPU (6
Since the data input circuit is equipped with a second AND circuit that inputs the code to the CPU, there is a delay in data input compared to the timing of manual data input of the CPLI as seen in conventional data input circuits. This eliminates the possibility of abnormal data being input.

[Brief explanation of the drawing]

FIG. 1 shows a conventional data input circuit, and FIG. 2 shows a block diagram as an embodiment of the circuit of the present invention. 1... CPU, 2... Latch circuit, 3... AND circuit, 4... AND circuit, 5... Latch circuit. Patent applicant: Nissin Electric Co., Ltd. Representative Patent Attorney Koji Onishi Figure 1 (c) 2 “4
(D) 1. Figure 3 (Input to CPU) Procedural amendment +', +: (method) % formula % 1981 Patent Application No. 19087 3 Person making amendment '11 ('l and Relationship between patent issuer I11s1
47 Umezu Takaune-cho, Ukyo-ku, Kyoto City, -/, U II 1st name) ($14) Nissin Electric Co., Ltd. Representative Masakatsu Yamawaki 4, Agent 6, Number of inventions to be increased by Masakatsu hli DI+ 07
, 1 between “mu” and “woshimezu” in line 10 of shell 5 of the specification subject to amendment
, FIG. 3 is a timing chart of the data input circuit of the present invention.

Claims (1)

[Claims] a first latch circuit that outputs a latch output based on a point strobe signal output from the CPU; a first AND circuit that is opened by the output of the latch circuit and outputs data to a second latch circuit; A second
a second latch circuit input to the AND circuit;
a second AND circuit that is started by the output of the latch circuit and inputs a data input signal from a CPU to the CPU.