JPS581354A - Sepeed-up conversion system - Google Patents

Abstract

PURPOSE:To simplify a circuit by using two D type flip-flops (DFF) when inserting one-bit additional data into N-bit input data and outputting speeded-up data. CONSTITUTION:Input data 3 is latched by an even-numbered DFF when a signal 2 frequency-divided by two at a fall of a data clock 1, and latched by an odd- numbered DFF at a fall of said signal 2. At a rise of a signal fs6 in phase with the clock obtained by multiplying a data clock by a factor of (N+1)/N, inserted data 7 is read out firstly and then the data latched by the even-numbered and odd-numbered DFFs are read alternately N times. This operation is repeated to insert one bit into N-bit input data at each time, thus performing speed-up conversion.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a speed-up method for asynchronously inserting additional information data into a data and PCM transmission device.

Previously, information data was inserted using KAM%FM.

In the case of digitization, methods are used to speed up the signal by synchronizing it with the PCM multiplexer's data, and in the asynchronous speed-up conversion method, The method of the conversion circuit has not been determined.

The present invention provides the present method with a simple basic configuration since the method of the conversion circuit has not been determined in the past in the asynchronous speed-up conversion method in the Data Communication System or P'CM Communication System. .

FIG. 1 shows a timing chart of the alternate speed upco/part system of this system. (31 input data to (1) data clock f.

The input data is latched into EVEN D-FF at the rising edge of fc72 (21), and ODD 1 at the falling edge of (2) f./2)-FF.
latches the input data. (The signal 61 is a signal f that is in phase with (N+1)/N times the fc of 11. At the rising edge 9 of the signal fs, the inserted data (7) is read out first, and then Times EVEN D-F'F',!:
0DI) The latched data of D-FF is called out alternately. By repeating this operation, input data N
It is possible to speed up conversion by inserting insertion data one bit at a time.

Inverse conversion on the receiving side tri [81 speeded up data is (6) fs The falling edge of fs is 9, and the clock (11) is frequency-divided by 2, and the rising edge of /2 is 9 and the receiving side E
VEN Read data into D-FF ((9) in FIG. 1), receive 1Ill1ODL at falling edge. Read data into D-FF ((10) in FIG. 1).

And the clock f in (6) has a phase match of 7 at the insertion position.
'(fs N/(N+1) times the clock (12)
(Receiving side EVEN D-FF and receiving side 0I in ,l)D
Read D-FF alternately. When the insertion data reaches the starting position, the insertion data is removed by reversing the reading order of the amount (g side EVBN D-F)' and the reception @ODD D-FF, and the original signal is generated like the signal (13). It is possible to restore the data.

FIG. 1 is a timing chart for the case of N-4.

In the conventional technology, the conversion circuit method for the asynchronous speed-up conversion method has not been determined, so in the case of the method of inserting 1 bit into the input data (N bits), according to this method, the input data is 2 D-F in memory
Since neither i''l nor I5 is used, the overall circuit configuration can be simplified.

[Brief explanation of drawings]

The figure shows fs1'P of this method alternate type #synchronized speed ag conversion method! - Reception timing chart. 1...Data clock fC 2...fC/2 clock 3...Input data 4...EIN D-Fk' latch data 5...0
f) i) D-FF latch data 6...Speed-up clock f. 7.-Insert data 8...Output 9...Receive @, VMN D-FF latch data 1
0... Receiving side ODD D-FF latch data 11...
・f,/2 clock 12...Receiving side clock fc1 16...Receiving side demodulated data N

Claims (1)

[Claims] t In digital communication or PCM communication, when inserting supervisor information or a digitized voice signal into the data bits of the digital communication or PCM communication, the data N bits (N-1, 2, 3...) In order to insert one bit of additional data such as the supervisor information or the digitized audio signal, the data bit is clocked by the clock f of the data bit. At the rise of the signal divided by 2, two D clips are generated.
Among the 70 blocks, one for even number data is latched by the FF. At the falling edge of D-FF, it latches into the D-FF for odd data of F and reads the data, and it takes one clock fc to output the speeded-up data □.
(N+1)/N times the in-phase clock f. The additional data is read at the rising edge of , and from the 2nd bit to the (N+1)th bit, the above EVEN
A speed-up conversion method characterized by reading and outputting FF and ODD D-FF data alternately.