JPS58129741U

JPS58129741U - tuner circuit

Info

Publication number: JPS58129741U
Application number: JP2568382U
Authority: JP
Inventors: 神津　光宏
Original assignee: 株式会社東芝
Priority date: 1982-02-26
Filing date: 1982-02-26
Publication date: 1983-09-02

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Brief explanation of the drawing]

第１図及び第２図は従来の電子選局チューナのブロック
図、第３図は第１図、第２図の各同調回路の一例を示す
回路図、第４図は第３図回路のバラクタ・ダイオードの
逆方向電圧Ｖ□対容量Ｃの特性図、第５図は第１図回路
を第３図の同調回路で構成した場合の回路図、第６図は
チューニング電圧発生回路の一例を示す回路図、第７図
は段間同調回路におけるバラクタ・ダイオードによる検
波作用を説明する回路図、第８図はバラクタ・ダイオー
ドの逆方向及び順方向特性を示す特性図、第９図は段間
同調回路に生じた検波電圧Ｅｏの局部発振回路用同調回
路への影響を説明する回路図、第１０図は本考案に係る
チューナ回路の第１実施例を示す回路図、第１１図はそ
の第２実施例を示す回路図、第１２図は第３実施例を示
す回路図である。１・・・チューナ回路、２・・・ＲＦ信号入力端子、３
・・・ＲＦ入力同調回路、４°・・・高周波増幅器、５
・・・段間同調回路、６・・・混合器、７・・・チュー
ニング電圧印加端子、８・・・局部発振回路用同調回路
、９・・・局部発振回路、１０・・・ＩＦ同調回路、１
１・・・ＩＰ出力端子、１２・・・バラクタ・ダイオー
ドの順方向特性、Ｌｌ・・・コイル、Ｃ□、Ｃ２・・・
コンデンサ、Ｄｏ・・・バラクタ・ダイオード、Ｒ，Ｒ
Ａ、　ＲＥ、　ＲＦ、、　ＲＦ、　Ｒ，”’抵抗、ぬ・
・・チューニング電圧、Ｈ・・・過大搬送波、ａ・・・
信号入力点、Ｉ□、Ｉ２・・・検波電流、Ｅｏ・・・検
波電圧、Ｄ。・・・ダイオード、Ｒｏ・・・抵抗。第５図第７図＆ｅｒＯｃｃFigures 1 and 2 are block diagrams of conventional electronic tuning tuners, Figure 3 is a circuit diagram showing an example of each tuning circuit in Figures 1 and 2, and Figure 4 is a varactor of the circuit in Figure 3.・Characteristic diagram of diode reverse voltage V□ vs. capacitance C. Figure 5 is a circuit diagram when the circuit in Figure 1 is configured with the tuning circuit in Figure 3. Figure 6 shows an example of a tuning voltage generation circuit. Circuit diagram, Figure 7 is a circuit diagram explaining the detection action by the varactor diode in the interstage tuning circuit, Figure 8 is a characteristic diagram showing the reverse and forward characteristics of the varactor diode, and Figure 9 is the interstage tuning circuit. A circuit diagram illustrating the influence of the detected voltage Eo generated in the circuit on the local oscillation circuit tuning circuit, FIG. 10 is a circuit diagram showing the first embodiment of the tuner circuit according to the present invention, and FIG. 11 is the second embodiment. FIG. 12 is a circuit diagram showing a third embodiment. 1... Tuner circuit, 2... RF signal input terminal, 3
...RF input tuning circuit, 4°...High frequency amplifier, 5
...Interstage tuning circuit, 6...Mixer, 7...Tuning voltage application terminal, 8...Tuning circuit for local oscillation circuit, 9...Local oscillation circuit, 10...IF tuning circuit ,1
1...IP output terminal, 12...Forward characteristics of varactor diode, Ll...coil, C□, C2...
Capacitor, Do... Varactor diode, R, R
A, RE, RF,, RF, R,”'Resistance, Nu・
...Tuning voltage, H...Excessive carrier wave, a...
Signal input point, I□, I2...detection current, Eo...detection voltage, D. ...Diode, Ro...Resistance. Figure 5 Figure 7 &erO cc

Claims

[Scope of utility model registration request]

In an electronic tuning tuner that uses a varactor diode in each tuning circuit and performs tuning by applying a tuning voltage to the varactor diode, a diode is inserted in the signal path for applying the tuning voltage to the varactor diode, and A tuner circuit characterized in that a bleeder resistor is connected between the diode and the varactor diode in parallel to the varactor diode.