JPS58128092A - Associative memory circuit - Google Patents

Abstract

PURPOSE:To form an associative memory circuit with less wiring number and possible for high density, large capacity and low cost, by forming the circuit using stored information in using P channel MIS transistors (TRs) and N channel MIS TRs. CONSTITUTION:The P channel MOS TR(hereinafter P-MOS)5 is connected to the 1st terminal 2 of the memory circuit 1 and the N channel MOS TR(hereinafter N-MOS)4 is connected to the 2nd terminal 3. In applying retrieval information to supply lines 12, 13 retrieval is executed for the associative memory circuits 8-11. When the stored information Q and the retrieval information S are coincident in the two associative memory circuits, e.g., 8, 9 forming one word, since no current flows to the corresponding 2nd retrieval result output terminal 14 or the terminal remains at a low potential, this state is detectable. Thus, the associative memory circuits can detect the word having the storage information coincident with the retrieval information, allowing to attain retrieval.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an associative memory circuit constructed using a p-channel MIS transistor and an n-channel MI8 transistor.

Conventional p-channel MIS) A simple configuration associative menu using transistors and n-channel MIS) transistors
As a memory circuit, there is a circuit shown in FIG. 1 (Japanese Patent No. 884472). In order to perform a retrieval operation between the memory information 11Q and the retrieval information S, the circuit company shown in FIG. A mismatch is being determined. As can be seen from this explanation, in the circuit shown in FIG. 1, it is essential to supply search information S and S to each associative memory circuit. This is because in semiconductor integrated circuits, the number of wires in a circuit is a major factor in determining the area occupied by the circuit, and the fact that there are many wires means that it is impossible to achieve higher density and larger capacity. This also means that it is not possible to lower prices.

In this way, in the conventional Sonji of this type, the search data S and S
It is necessary to supply each circuit with at least two wires, which has the disadvantage that it is difficult to miniaturize the circuit, especially to increase the density, capacity, and cost of semiconductor integrated circuits.

The present invention) uses p-channel MIS transistors and n-channel MIS transistors to store information Q and Q.
The purpose of the present invention is to realize an associative memory circuit that requires a small number of wiring lines and can achieve high density, large capacity, and low cost.

FIG. 2 shows an embodiment of the present invention, which is a 1-bit content addressable memory circuit. In FIG. 2, 1 is a memory circuit having a first terminal 2 from which stored information Q can be taken out and a second terminal 3 from which Q can be taken out, and 4 is an n-channel first MOS transistor. Ashi, 5
is the second P-channel MOS transistor,
6 is a first control line, and 7 is a first search result output terminal.

The operation will be explained below using FIG. 1 and FIG. The circuit in FIG. 2 has a P-channel MOS connected to the first terminal 2 of the memory circuit 1.
A transistor (hereinafter referred to as p-MOS) 5, an n-channel MOS) transistor (hereinafter referred to as W
-MOS) 4 are connected, but the same explanation can be applied to the reverse case as well. Furthermore, memory circuits from which stored information Q and Q can be retrieved are extremely common, and all MOS static type memory circuits fall under this category.

The search operation of this content addressable memory circuit will be explained. A potential corresponding to the search information S is applied to the first control line 6 . In addition,
All of the following explanations will be made using positive logic, but this can be similarly explained using negative logic.

■ When search information S-0 and storage information Q=O, p-MOS
5 is turned on, the stored information Q=O is delivered to the first search result output terminal 7.

■ When search information S-0 and storage information Q = 1, p-MOS
5 is on, and the stored information Q=1 is delivered to the first search result output terminal 7.

■ When search information S=1 and storage information Q=0, n-MOS
4 is turned on, and the negative Q=1 of the stored information is output to the first search result output terminal 7.

■ When search information S-1 and storage information Q = 1, n-MOS
4 is on, and the negative Q-O of the stored information is output to the first search result output terminal 7.

From the potential of the search result output terminal 7, it can be determined whether Q and S match or do not match, and it can be seen that the search operation can be accomplished.

FIG. 3 shows the connection relationship when a plurality of associative memory circuits of the present invention shown in FIG. 2 are arranged in a matrix, and is an example of an associative memory circuit having a 2 word x 2 bit configuration. In FIG. 3, 8 to 11 are the associative memory circuits shown in FIG. 2, 12 and 13 are search information supply lines, and 14 and 15 are the second search results for each word. It is an output terminal. The terminal is 6.7 in Figure 2.
corresponds to, for example, 6 and 7 of the associative memory circuit 8 in FIG. Associative memory circuits 8 and 9 constitute one word, and 10
and 11 make up one word. The search operation of this matrix-arranged associative memory circuit will be described below with reference to FIG. Furthermore, the following explanation can be similarly applied to any word X bit configuration. supply, il
When search information is applied to 1z'II 13, each content addressable memory circuit 8-11 performs a search operation as described in the embodiment shown in FIG.

If the stored information Q and the search information S match in both of the two content addressable memory circuits 8 and 9 constituting one word, then no current flows to the corresponding second search result output terminal 14, or Alternatively, this condition is detectable because it remains at a low potential. In this way, in this associative memory circuit,
Words with stored information that match the search information can be detected, and the search operation can be accomplished.

FIG. 4 shows another embodiment of the present invention.
One n-MOS is added to the content addressable memory circuit shown in the figure. In Figure 4, 16 is the added n-MO
17 is the second control line, and 18 is the third control line. In this embodiment, an example in which a loop MO8 is added will be described, but a circuit similar to this can also be constructed using P-MOS. During the search operation in this embodiment, the potentials shown in Table 2 are applied to the first search result output terminal 7. Therefore, the added rule MO 816 is the storage information Q and the search information S.
is turned on when the two control lines are different, and a current path between the second control line 17 and the third control line 18 is formed. Whether or not a current path is formed can be detected very easily, and by detecting this, it is possible to determine whether the stored information Q and the search information S match or do not match, and the search operation is accomplished.

FIG. 5 shows the connection relationship when a plurality of associative memory circuits of the present invention shown in FIG. 4 are arranged in a matrix, and is an example of an associative memory circuit having a 2 word x 2 bit configuration. In FIG. 5, 19 to 22 are associative memory circuits shown in FIG.

The associative memory circuits 19 and 20 constitute one word, and the associative memory circuits 21 and 22 constitute one word. 23 is a connection between the second control lines of the associative memory circuits 19 and 20;
4 is the third control line of the associative memory circuit 19.20, and 25 is the second control line of the associative memory circuit 21.22.
The control lines 26 are connected to the third control lines of the associative memory circuits 21 and 22. As for the terminals, 6.17.18 in FIG. 4 corresponds to 6.17°18 of the associative memory circuit 19 in FIG. 5, for example. The search operation of the content addressable memory circuit will be described below with reference to FIG. 5, but the following explanation can be similarly applied to any word X-bit configuration. Supply line 12. When search information is applied to 13, each associative memory circuit 19-20 performs a search operation as explained in the embodiment of FIG.

If the stored information and search information do not match in at least one of the two associative memory circuits configuring one word, for example 19.20, the corresponding two common lines 23
．． A current path is formed between 24. It is extremely easy to detect whether a current path is formed, and by detecting this, it becomes clear whether the stored information of the word matches or does not match the search information, and the search operation can be performed. achieved.

FIG. 6 shows still another embodiment of the present invention, in which one loop MO is added to the associative memory circuit of the embodiment of FIG.
8 is added. In FIG. 6, 27 is the added loop MO8, and 28 is the fourth control line. In this embodiment, an example in which an n-MOB is added will be described, but a circuit similar to this can also be constructed using a p-Mo8.

The search operation in this embodiment will be explained below with reference to FIG. In this content addressable memory circuit, when the loop MO 827 is on, the search operation is exactly the same as that shown in FIG. When the n-MOB 27 is off, a current path between the second control line 17 and the third control line 18 is hardly formed, regardless of whether the stored information Q and the search information S match or do not match. This fact means that by controlling the on/off state of the n-MOB 27, the corresponding associative memory circuit can be included in the search operation or excluded from the search operation. n-MO
B 270 is switched on or off by the potential applied to the fourth control line 28.

FIG. 7 shows the connection relationship when a plurality of associative memory circuits of the present invention shown in FIG. 6 are arranged in a matrix, and is an example of an associative memory circuit having a 2 word x 2 bit configuration. be. In FIG. 7, numerals 29 to 32 are associative memory circuits shown in FIG. Associative memory circuits 29 and 3
0 constitutes one word, and 31 and 32 constitute one word. 33 is a connection between the fourth control lines of the content addressable memory circuits 29 and 31, and 34 is a connection of the fourth control lines of the content addressable memory circuits 29 and 31.
0. 32 fourth control lines are connected. For example, the terminal '6t 17.18.28 in FIG. Corresponds to 17.18.28. The search operation of the present associative memory circuit will be explained below with reference to FIG.
The same can be done for the bit configuration.

Give wll to the common lines 33 and 34, and connect each associative memory circuit 2
The search operation when the n-MOs 827 in 9 to 32 are turned on is the same as in the embodiment shown in FIG. 5, and can be easily understood. When 1lO1 is given in any combination to the common lines 33 and 34, in the associative memory circuit connected to the common line 33 or 34 to which l1Ofi is given, the 6th
As can be seen from the description of the embodiment of the figure, n-MOB 27
When the associative memory circuit is turned off, that content addressable memory circuit is excluded from the search target. By using the present associative memory circuit in this way, it is possible to perform a search operation using any bit as a search target.

This ability to specify a search target is generally an extremely important function in associative memory circuits.

As explained above, since an associative memory circuit that utilizes the stored information Q using the p-MOB and the Lou MO8 can be realized, the following advantages arise.

(1) The number of wires required to supply search information has been reduced.

(2) Therefore, the circuit can be made smaller.

(3) In semiconductor integrated circuits, the number of wires in a circuit is a major factor determining the area occupied by the circuit.
According to the present invention, it is possible to increase the density and capacity of an associative memory circuit.

(4) Since higher density and larger capacity have become possible, the cost of associative memory circuits can be reduced.

[Brief explanation of drawings]

FIG. 1 shows a conventional inductive memory circuit. FIG. 2 shows an embodiment of the present invention, in which a 1-bit content addressable memory circuit is shown, and FIG. 3 shows a 2-bit content addressable memory circuit.
This is an embodiment in which a matrix array of word x 2 bits is used. Fig. 4 shows another embodiment of the present invention, in which a 1-bit content addressable memory circuit is used, and Fig. 5 shows an embodiment in which the content addressable memory circuit shown in Fig. 4 is arranged in a matrix of 2 words x 2 bits. be. FIG. 6 shows still another embodiment of the present invention.
Bit content addressable memory circuit FIG. 7 is an embodiment in which the content addressable memory circuit of FIG. 6 is arranged in a matrix of 2 words x 2 bits. The first MOS transistor of the channel, 15...
...Second MOS of pf Jannel) transistor,
6......First control line, 7...
...First search result output terminal, 8 to 11...
...Associative memory circuit, 12.13...
・Supply line, 14... Second search result output terminal, 16... Third MOS of channel) Transistor, 17... ...Second control line, 18...Third control line, 19~
22・・・・・・・Associative memory channel, −η−・nee・
--- Second control line, 27 --- Le channel fourth MOS transistor, 28 ---
...Fourth control line, 29-32...
Associative memory circuit, 33.34...Common line. Figure 1 Figure 3 Figure 4 Figure 5 Figure 25

Claims (3)

[Claims] (1) A first terminal that can store 1-bit information Q and retrieve the stored information Q; and
a memory circuit having a second terminal from which negation information Q can be extracted, and either the first or second terminal of the memory circuit and the first MI of the channel are connected.
the first MIS to which the source of the S transistor is connected; the first or second terminal of the memory circuit to which the source of the transistor is not connected; and the p-channel second MIS
Connect the drains of the transistors and connect the first MIS
) The drain of the transistor and the source of the second MIS are commonly connected to the first search result output terminal, and the drain of the transistor is connected to the first search result output terminal.
) A content addressable memory circuit characterized in that the gates of the transistors are commonly connected to a first control line. (2) A first terminal that can store 1-bit information Q and retrieve the stored information Q; and
a memory circuit having a second terminal from which negative information i can be retrieved, and one of the first or second terminals of the memory circuit and the first MI of the channel.
Connect the source of the S transistor and connect the first MIS)
The node xt of the transistor is connected to the first or second terminal of the memory circuit and the second MI of the P channel.
Connect the drains of the S transistors and connect them to the first MI
D) The drain of the transistor and the second MIS;) The source of the transistor is commonly connected to the first search result output terminal;
The gates of the S transistors are commonly connected to the first control line, the first search result output terminal is connected to the gate of the third MIS transistor of the channel or p channel, and the gate of the third MIS transistor is connected to the first control line. A content addressable memory circuit characterized in that a source is connected to a second control line, and a drain of the third MI8 transistor is connected to a third control line. (3) It has a first terminal that can store one piece of information Q and can retrieve the stored information Q, and a second terminal that can retrieve the negative information δ of the stored information Q. a memory circuit, one of the first or second terminals of the memory circuit and a first M of the n channel;
l8 Connect the source of the transistor and connect the first MIS
The source of the transistor is connected to the first or second terminal of the memory circuit and the second MI of the P channel.
S) Connect the drain of the transistor and connect the first MIS
The drain of the transistor and the source of the second MIS transistor are commonly connected to the first search result output terminal, and the first MIS transistor and the second MIS transistor are
) The gates of the transistors are commonly connected to the first control line, the first search result output terminal is connected to the gate of the n-channel transistor or the 23rd Ml8 transistor of the n-channel, and the source of the 30th Ml8 transistor is connected to the 2 control line, the drain of the third ONIB transistor is connected to the third control line, and a 9-channel or P-channel transistor is connected between the source of the third ONIB transistor and the second control line. In order to insert 4 MrS transistors, connect the source of the 3rd MIS transistor and the drain of the 4th MIS transistor, and
S) An associative memory circuit characterized in that the source of the transistor is connected to the second control line, and the gate of the fourth MI8 transistor is connected to the fourth control line.