JPS5812752B2 - Hand-made Thai Hatsukousouchi - Google Patents

Hand-made Thai Hatsukousouchi

Info

Publication number
JPS5812752B2
JPS5812752B2 JP50028185A JP2818575A JPS5812752B2 JP S5812752 B2 JPS5812752 B2 JP S5812752B2 JP 50028185 A JP50028185 A JP 50028185A JP 2818575 A JP2818575 A JP 2818575A JP S5812752 B2 JPS5812752 B2 JP S5812752B2
Authority
JP
Japan
Prior art keywords
insulating layer
substrate
semiconductor
light
hole
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP50028185A
Other languages
Japanese (ja)
Other versions
JPS51101486A (en
Inventor
中田俊武
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanyo Electric Co Ltd
Original Assignee
Sanyo Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanyo Electric Co Ltd filed Critical Sanyo Electric Co Ltd
Priority to JP50028185A priority Critical patent/JPS5812752B2/en
Publication of JPS51101486A publication Critical patent/JPS51101486A/ja
Publication of JPS5812752B2 publication Critical patent/JPS5812752B2/en
Expired legal-status Critical Current

Links

Description

【発明の詳細な説明】 本発明は半導体発光装置に関する。[Detailed description of the invention] The present invention relates to a semiconductor light emitting device.

本発明は、更に詳しくは、第1導電型半導体基板と、該
基板表面に設けられた有孔絶縁層と、該絶縁層の孔と整
合して上記基板表面部に設けられた第2導電型領域とか
らなる半導体発光装置に於て、上記絶縁層の孔を通して
放出される光の発光輪郭をシャープにせんとするもので
ある。
More specifically, the present invention provides a first conductive type semiconductor substrate, a perforated insulating layer provided on the surface of the substrate, and a second conductive type semiconductor substrate provided on the substrate surface in alignment with the holes of the insulating layer. In a semiconductor light emitting device comprising a region, the light emission contour of light emitted through the hole in the insulating layer is made sharp.

第1図は従来のこの種装置を示し、1はN型燐化ガリウ
ム基板、2は該基板表面に設けられ、孔3を有する絶縁
層、4は該絶縁層の孔3と整合して基板1の表面部に設
けられたP型領域である。
FIG. 1 shows a conventional device of this type, in which 1 is an N-type gallium phosphide substrate, 2 is an insulating layer provided on the surface of the substrate and has a hole 3, and 4 is a substrate that is aligned with the hole 3 in the insulating layer. This is a P-type region provided on the surface of 1.

P型領域4は、例えば絶縁層2の孔3を利用した選択拡
散技術又は選択イオン注入技術によ9絶縁層2の孔3と
整合的に形成される。
The P-type region 4 is formed in alignment with the hole 3 of the insulating layer 2 by, for example, a selective diffusion technique using the hole 3 of the insulating layer 2 or a selective ion implantation technique.

5はN型基飯1とP型領域4との境界が作るPN接合で
あり光放出に寄与する。
5 is a PN junction formed by the boundary between the N-type substrate 1 and the P-type region 4, which contributes to light emission.

絶縁層2は、装置の製造過程に於て、P型領域4の区域
、即ち発光パターン区域を決めるために使用され、ある
いは、P型領域4に連なる配線電極膜の敷設面として利
用される。
The insulating layer 2 is used in the manufacturing process of the device to define the area of the P-type region 4, that is, the light-emitting pattern area, or as a surface on which a wiring electrode film connected to the P-type region 4 is laid.

然るに上記従来装置にあっては、絶縁層2が存在するに
も拘らず、発光パターンがぼやけるという欠点があった
However, the conventional device described above has the disadvantage that the light emitting pattern is blurred despite the presence of the insulating layer 2.

絶縁層2の材質としては、半導体技術分野では窒化シリ
コンや酸化シリコンが好適例として知られているが、こ
れら絶縁層は全て、かなりの膜厚にても透光性を示し、
従って、絶縁層2の孔3を経る中心放出光6の他に、孔
3周辺の絶縁層2を経る周辺放出光7が存在し、発光パ
ターンは周囲がにじんだ様にぼやける。
Silicon nitride and silicon oxide are known as suitable materials for the insulating layer 2 in the semiconductor technology field, but all of these insulating layers exhibit light transmittance even at a considerable thickness.
Therefore, in addition to the center emitted light 6 that passes through the hole 3 of the insulating layer 2, there is peripheral emitted light 7 that passes through the insulating layer 2 around the hole 3, and the light emission pattern becomes blurred as if the periphery is blurred.

周辺放出光7はP型領域4から直接絶縁層2に入るもの
、基板1の底面で反射されて絶縁層2に入るものがある
が、何れの場合にも、基板1の結晶が放出光に対して透
明な関係にある時、例えば燐化ガリウム結晶と緑色放出
光との組合わせ時には、放出光が結晶中を通過し易く、
従って絶縁層2を経る周辺放出光7が増大し、発光パタ
ーンのぼやけ現象は助長される。
The peripheral emitted light 7 may enter the insulating layer 2 directly from the P-type region 4, or may be reflected from the bottom surface of the substrate 1 and enter the insulating layer 2, but in either case, the crystal of the substrate 1 is exposed to the emitted light. When the relationship is transparent, for example, when a gallium phosphide crystal and green emitted light are combined, the emitted light easily passes through the crystal.
Therefore, the peripheral emitted light 7 passing through the insulating layer 2 increases, and the phenomenon of blurring of the light emitting pattern is promoted.

本発明は斯る点に鑑みてなされたもので、第2図Eの実
施例に示す如く、基板1表面の少なくとも絶縁層の孔3
周辺は基板結晶のバンドギャップより小さいバンドギャ
ップを有する半導体層8に変成されてなる点に特徴を有
する。
The present invention has been made in view of this point, and as shown in the embodiment shown in FIG.
The periphery is characterized in that it is transformed into a semiconductor layer 8 having a bandgap smaller than that of the substrate crystal.

尚第1図と同一部分には同一番号が付されている。Note that the same parts as in FIG. 1 are given the same numbers.

本実施例装置に於て、絶縁層2に向う周辺放出光7はバ
ンドギャップのより小さい半導体層8により吸収あるい
は反射されて外部には放射されない。
In the device of this embodiment, the peripheral emitted light 7 directed toward the insulating layer 2 is absorbed or reflected by the semiconductor layer 8 having a smaller bandgap and is not emitted to the outside.

即ち半導体層8は光遮蔽層として機能し、従ってこの時
の発光パターンは中心放出光6のみにより構成されにじ
みはなくなる。
That is, the semiconductor layer 8 functions as a light shielding layer, and therefore the light emission pattern at this time is composed only of the centrally emitted light 6, and there is no bleeding.

第2図A乃至Eは上記実施例装置の製造工程を示す。FIGS. 2A to 2E show the manufacturing process of the above embodiment device.

以下この工程順に説明すれば、先ず第2図Aの工程に於
て、窒素を含んだN型燐化ガリウム基板1表面上の所定
領域にホトレジスト9を被着し、次いでイオン注入法に
より基板1表面に砒素イオンを注入する。
To explain this process order below, first, in the process shown in FIG. Arsenic ions are implanted into the surface.

ホトレジスト9は約1μの厚さに被着され、砒素イオン
が上記所定領域の基板表面下に注入されるのを阻止する
Photoresist 9 is deposited to a thickness of about 1 micron to prevent arsenic ions from being implanted below the substrate surface in the predetermined areas.

従って上記所定領域を除いて、砒素イオン注入領域10
が形成される。
Therefore, except for the above predetermined region, the arsenic ion implantation region 10
is formed.

該領域の好ましい深さは1000Å以上である。The preferred depth of this region is 1000 Å or more.

次いで第2図Bの工程に於て、ホトレジスト9が除去さ
れ、基板表面に約5000Å厚さの絶縁層2が形成され
る。
Next, in the step shown in FIG. 2B, the photoresist 9 is removed and an insulating layer 2 with a thickness of about 5000 Å is formed on the substrate surface.

次いで第2図Cの工程に於て、砒素イオン注入領域10
上にのみ絶縁層2を残すべく該絶縁層に孔3が設けられ
る。
Next, in the step shown in FIG. 2C, the arsenic ion implantation region 10 is
Holes 3 are provided in the insulating layer so that the insulating layer 2 remains only on top.

続く第2図Dの工程に於て、基板全体が800℃で熱処
理される。
In the subsequent step shown in FIG. 2D, the entire substrate is heat treated at 800°C.

斯る熱処理は、砒素イオン注入領域に於て、当初の基板
結晶である燐化ガリウムGapが砒化燐化ガリウムGa
Asl−xPxに再結晶化されるのを促す。
Such heat treatment causes the initial substrate crystal gallium phosphide Gap to change to gallium arsenide phosphide Ga in the arsenic ion implantation region.
Promote recrystallization to Asl-xPx.

これにより砒素イオン注入領域は基板1結晶のバンギャ
ップより小さいバンドギャツプを有する半導体層8に変
成される。
As a result, the arsenic ion implanted region is transformed into a semiconductor layer 8 having a band gap smaller than that of the substrate 1 crystal.

最後に第2図Eの工程に於て、絶縁膜2の孔3を利用し
た亜鉛の選択拡散技術によりP型領域4が約2μの深さ
だけ設けられ装置が完成する。
Finally, in the step shown in FIG. 2E, a P-type region 4 is provided to a depth of approximately 2 .mu.m by a selective zinc diffusion technique using the holes 3 in the insulating film 2, and the device is completed.

以上の説明から明らかな如く、本発明によれば、半導体
基板上に設けた有孔絶縁層の孔を介して放出光を取り出
す装置に於て、上記基板表面の少なくとも絶縁層の孔周
辺を光遮蔽効果を有する半導体層に変成したものである
から、簡単な構造にして上記絶縁層を通る周辺放出光が
無くなり、発光パターンは絶縁層の孔を通る中心放出光
のみにより形成され、その輪郭がシャープなものとなる
As is clear from the above description, according to the present invention, in a device for extracting emitted light through a hole in a porous insulating layer provided on a semiconductor substrate, at least the vicinity of the hole in the insulating layer on the surface of the substrate is exposed to light. Since it has been transformed into a semiconductor layer that has a shielding effect, it has a simple structure and there is no peripheral emitted light passing through the insulating layer, and the light emitting pattern is formed only by the central emitted light passing through the holes in the insulating layer, and its outline is It becomes sharp.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来例を示す断面図、第2図A乃至Eは本発明
実施例を示す工程別断面図である。 1・・・・・・N型基板、4・・・・・・P型領域、2
・・・・・・絶縁層、8・・・・・・変成された半導体
層。
FIG. 1 is a sectional view showing a conventional example, and FIGS. 2A to 2E are sectional views showing steps of an embodiment of the present invention. 1...N-type substrate, 4...P-type region, 2
...Insulating layer, 8...Transformed semiconductor layer.

Claims (1)

【特許請求の範囲】[Claims] 1 第1導電型半導体基板と、該基板表面に設けられた
有孔絶縁層と、該絶縁層の孔と整合して上記基板表面部
に設けられた第2導電型領域とからなり、上記基板表面
の少なくとも上記絶縁層の孔周辺は上記基板結晶のバン
ドギャップより小さいバンドギャップを有する半導体層
に変成されてなる半導体発光装置。
1 Consisting of a first conductivity type semiconductor substrate, a perforated insulating layer provided on the surface of the substrate, and a second conductivity type region provided on the surface of the substrate in alignment with the holes of the insulating layer, the substrate A semiconductor light emitting device, wherein at least a portion of the surface of the insulating layer around the hole is transformed into a semiconductor layer having a bandgap smaller than the bandgap of the substrate crystal.
JP50028185A 1975-03-04 1975-03-04 Hand-made Thai Hatsukousouchi Expired JPS5812752B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP50028185A JPS5812752B2 (en) 1975-03-04 1975-03-04 Hand-made Thai Hatsukousouchi

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP50028185A JPS5812752B2 (en) 1975-03-04 1975-03-04 Hand-made Thai Hatsukousouchi

Publications (2)

Publication Number Publication Date
JPS51101486A JPS51101486A (en) 1976-09-07
JPS5812752B2 true JPS5812752B2 (en) 1983-03-10

Family

ID=12241631

Family Applications (1)

Application Number Title Priority Date Filing Date
JP50028185A Expired JPS5812752B2 (en) 1975-03-04 1975-03-04 Hand-made Thai Hatsukousouchi

Country Status (1)

Country Link
JP (1) JPS5812752B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60191751U (en) * 1984-05-30 1985-12-19 富士重工業株式会社 chain tensioner

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5025196A (en) * 1973-06-28 1975-03-17

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5025196A (en) * 1973-06-28 1975-03-17

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60191751U (en) * 1984-05-30 1985-12-19 富士重工業株式会社 chain tensioner

Also Published As

Publication number Publication date
JPS51101486A (en) 1976-09-07

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