JPS5812600B2 - electronic musical instruments - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an electronic musical instrument, and more particularly to an electronic musical instrument that can appropriately switch and change the sound series to produce sound effects similar to when a plurality of musical instruments are played in concert.

In digitally processed electronic musical instruments equipped with a large number of keys,
In order to create a configuration that can produce multiple sounds at the same time, limit the maximum number of simultaneous sounds to a specific number that is smaller than the number of keys, create a sound generation channel corresponding to this specific number, and select a sound by pressing a key. It has been proposed to allocate the sound tones to appropriate channels among the above-mentioned sound generation channels, and to generate the corresponding musical tones from the allocated channels.

A device called a key assigner performs the above-mentioned assignment processing, and this key assigner assigns key information representing the pressed key (hereinafter referred to as an operation key) to one of the plurality of sound generation channels. A desired musical tone is generated from a musical tone forming circuit corresponding to the channel based on the key information.

However, in the above-mentioned conventional electronic musical instruments, key information representing a certain key is assigned to only one of a plurality of sound generation channels, and the musical tone signal corresponding to the key information is generated. For example, when performing an ensemble of a piano and a pipe organ, a sound effect can be obtained in which multiple tones of different tones are simultaneously produced for one key information. I couldn't do that.

This can be achieved by connecting a musical tone forming circuit that generates musical tones of other tones in parallel to the musical tone forming circuit of all the sound generating channels. Providing a plurality of devices in parallel would complicate the device and significantly increase the cost.

Further, in the above-mentioned conventional electronic musical instruments, the sound generation channels and musical tone forming circuits are fixed, so that they have various drawbacks such as the inability to change the number of sound generation sequences.

Therefore, an object of the present invention is to provide an electronic musical instrument in which the sound generation series (sound generation channels) can be changed very easily, thereby easily producing sound sound effects similar to those obtained when an ensemble of different types of musical instruments is performed.

Another object of the present invention is to provide an electronic musical instrument that can produce sound effects similar to an ensemble performance without adding a special sound generation channel.

In order to achieve such an object, the present invention controls whether the key information assigned to the sound generation assignment channel of the key assigner is supplied to one or more of the plurality of sound generation channels. The number of series can be freely changed within the fixed number of sound generation channels.

Hereinafter, the electronic musical instrument according to the present invention will be explained in detail using the drawings.

FIG. 1 is a block diagram schematically showing the overall configuration of an embodiment of an electronic musical instrument according to the present invention, and particularly shows a case in which the present invention is applied to an electronic musical instrument using a synthesizer-type musical tone forming circuit. Broadly speaking, out of the key switches provided for each key, the key switch that is operated (close operation for make contacts, open operation for break contacts) by the key press is detected, and this detected key switch A key coder 100 that generates a coded signal representing a key code KC, and a sound generation channel (much fewer than the number of keys) that can simultaneously sound the key code KC supplied from the key coder 100.

); and a key assigner 300 comprising a channel processor 200 that executes an operation of assigning to any one of the sound generation assignment channels corresponding to a key code/tone pitch voltage converting section 400, a tone pitch voltage KV sent from the key code/tone pitch voltage converting section 400, and the channel processor 2.
00 key-on state memory 204 and a tone control signal TM to be described later. (2) For the musical tone forming section 600 and the musical tone forming circuit 600 that generate musical tone signals corresponding to the key-on signal KO and the tone control signal TM for each sound generation channel,
It is comprised of a musical tone control signal memory 700 that generates musical tone control signals for setting and controlling the state of generated musical tones, and a timing signal generating section 800 that supplies various timing signals to each of the aforementioned sections.

In the key coder 100, a large number of key switches 10
A key switch circuit 102 having 1a to 101n is provided, and each of the key switches 101a to 101n of this key switch circuit 102 is divided into a plurality of blocks (for example, a group for each octave), and the key switches 101a to 101n in each block are Each key switch can be set to multiple notes (e.g. C).
, C#, D, . Wirings N1 to Nm are drawn out for each note, and the other terminal (fixed terminal) b side is commonly connected to each block, and wiring B1 to Bl is drawn out for each block.

Therefore, in this key switch circuit 102, each of the key switches 101a to 101n is arranged between each matrix at each intersection of a matrix (matrix wiring) in which block wirings B1 to Bl are "rows" and note wirings N1 to Nm are "columns". are connected to each other.

As a result, the total number of wires drawn out from the key switch circuit 102, that is, the total number of wires of the block wires B1 to Bl and the note wires N1 to Nm, is equal to the total number of wires drawn out from the key switch circuit 101a.
The number is much smaller than that of ~101n.

For example, if the number of all key switches 101a to 101n is [Xm
If there are j pieces, the key switch circuit 10 in this case is
The total number of wires drawn out from 2 is the number of notes (m) + the number of blocks (l), and the number is "m+l".

Each key switch 101a to 101n of the key switch circuit 102 configured in this way is connected to the note wiring N1 to Nm.
It is connected to the note detection circuit 103 via the block detection circuit 103, and is connected to the block detection circuit 103 via the lock wiring lines B1 to Bl. 104.

In this case, the detection of all operating key switches among all the key switches 101a to 101n is completed by sequentially executing several types of detection operation states (hereinafter simply referred to as states).

The first state ST1 is transmitted from the note detection circuit 103 to all the key switches 1 via the note wiring N1 to Nm.
A signal is applied to the movable contact side a of 01a to 101n, and is passed through the fixed contact side b of only the key switch in operation to the block wiring B1 of the block to which the key switch in operation belongs.
The applied signal is derived from ~Bl, and this derived signal is supplied to the block detection circuit 104 and stored.

This will tell you which blocks are active (turned on).
The presence of one or more key switches is detected.

Note that the block detection circuit 10 in this first state
The storage timing of No. 4 is determined by the first state signal supplied from the state control circuit 105 operating in synchronization with the timing signal generating section 800.

When the storage operation of the block detection circuit 104 is completed, the state control circuit 105 detects this and controls the second state.

Next, in the second state ST2, one block is extracted from among the blocks (one block or a plurality of blocks) stored in the block detection circuit 104 according to a predetermined priority order, and the block detection circuit 104 extracts one block according to a predetermined priority order.
Block wiring B1 corresponding to the block extracted from 4
A signal is applied to the fixed contact b side of each key switch included in the block through B7, thereby transmitting the signal from the note wiring N1 to Nm on the movable contact a side of the key switch of each note in the block. It is derived and stored in the note detection circuit 103.

In this way, the operating key switches 101a to 1
The signal from the block detection circuit 103 is transmitted only to the note wirings N1 to Nm corresponding to 01n, and by storing this signal in the note detection circuit 103, the operating key switch ( one or more notes) will be detected.

Further, the block signal extracted by the block detection circuit 104 is converted into a block code signal (hereinafter referred to as block code BC) of multiple bits (3 bits in this case) representing the block, and is sent to the sample hold circuit 104.
6 and store it.

Note that the block detection circuit 10 in this second state
4.1 block extraction timing and note detection circuit 1
The storage timing in 03 is determined by the second state signal supplied from the state control circuit 105, as in the case of the first state described above.

When the storage operation of the note detection circuit 103 is completed, the state control circuit 105 detects this and controls the third state.

Next, the third state ST3 is an operating state following the second state, in which the note (one or more) stored in the note detection circuit 103 in the second state is synchronized with the system clock and is The sample and hold circuit 106 sequentially extracts the note signals according to a predetermined priority order and converts the extracted note signals into a multi-bit (4 bits in this case) note code signal (hereinafter referred to as note code NC) representing the note. will be supplied sequentially.

Since this third state is executed only for notes stored in the note detection circuit 103, no time is wasted.

For example, if three types of notes are stored in the note detection circuit 103, the third state regarding a certain block is completed in three clock times.

When all the note code signals stored in the note detection circuit 103 are read out, the state control circuit 103
5 detects this and controls to the next state.

In this case, if the block signal is still stored in the block detection circuit 104, the second state and the third state are
Returning to control of the states, these states are executed in the same manner as described above.

Furthermore, if there is no memory of a block signal in the block detection circuit 104, the charge remaining in the block wirings B1 to BA of the key switch circuit 102 (the stray capacitance of the wiring or the minute capacitors connected to each wiring is charged) After resetting by discharging all the charges (charges accumulated), the state returns to the first state.

On the other hand, the sample and hold circuit 106 stores and holds the block code BC supplied from the block detection circuit 104 in the second state, and outputs it in synchronization with the note code NC supplied from the note detection circuit 103.

Therefore, the sample and hold circuit 106 sends out a key code KC having a 7-bit configuration in which the block code BC and the note code NC are combined, and it is possible to easily identify the operating key inch by this key code KC. .

In this way, the first state ST1 → second state ST2 →
Steps are performed in the third state ST3, etc., but when the block detection circuit 104 has sent out the block codes BC related to all the blocks initially stored and finished sending out the note code NC related to the note of the operation key switch in the last block. , block detection circuit 104
Since the memory of the note detection circuit 103 is completely extracted and disappears, this causes the fourth state STo
1 In other words, it becomes a standby state.

Then, the key switch circuit 102 and the note detection circuit 10
After confirming that all the operations of 3 and the block detection circuit 104 have been reset, the system returns to the first state ST1, and then returns to the second state ST2 and the third state ST2 as described above.
By repeating the state ST3 and reaching the fourth state STo, that is, the standby state, the detection operation of all the key switches is repeated once.

The key code KC sent from the sample hold circuit 106 of the key coder 100 is transmitted to the channel processor 2.
00, where the channels forming the musical tone signal are assigned.

In this case, the key code KC sent from the sample and hold circuit 106 is held for a certain period of time, and this holding time corresponds to the operating time during which one allocation process is executed in the channel processor 200.

- Also, this key coder 100 converts all the operated key switches into corresponding key codes KC and sends them to the corresponding key code KC.
6.

This signal X is used in channel processor 200 for key-off detection.

Table 1 shows an example of the contents of the block code BC and note code NC of the key code KC sent from the key coder 100.

Next, the channel processor 200 includes a key code memory 201, a key on/off detection circuit 202, a truncate circuit 203, and a key press state memory 204.

The key code memory 201 is provided with a specific number of storage circuits corresponding to a plurality of sound generation assigned channels corresponding to the number of sound generation channels that can be sounded simultaneously, and this storage circuit is conveniently constructed with a circular shift register.

In this case, the number of channels assigned for sound generation is A1 key code K
Assuming that the number of bits of C is B, an A-stage (1 stage = B bits) shift register having B storage units is used, and the stored (already assigned) key code KC is transferred by a clock pulse. The signals are sequentially shifted and sent out in a time-division manner to be used as control signals for generating musical waveforms, and are fed back to the input side of the shift register for circulation.

The key-on/off detection circuit 202 detects the input key code KC supplied from the key coder 100 and the key code memory 2.
Compares all stored key codes KC that are sequentially sent out from 01 in a time-sharing manner, and if they match, the input key code KC is
It is assumed that the same key code KC has already been assigned to a certain channel and is prevented from being stored in the key code memory 201, that is, the channel assignment is stopped.

Furthermore, if the above comparison results do not match, it means that a new key has been operated, so this input key code K
C is stored in all vacant channels of the key code memory 201.

Furthermore, if the above comparison results do not match and other key codes KC have already been assigned to all channels, the truncate circuit 203 assigns the note whose attenuation has progressed the most among the notes that have already been released. The key code KC stored in this channel is controlled to be forcibly rewritten to the input key code KC.

In addition, this key-on/off detection circuit 202 supplies the assignment state of the input key code KC to each channel to the key press state memory 204 for storage, and controls the sound generation operation of each channel, which will be described later, based on the readout output. At the same time, the key release is detected and the key press state memory 20 is stored.
The stored contents of the corresponding channel No. 4 are changed, and the sound generation of that channel is terminated while following predetermined conditions, that is, controlling the sound generation by gradually attenuating it.

In the subsequent operation, an empty channel is selected from the contents stored in the key press state memory 204, and an input key code KC is stored in the stage of the corresponding channel in the key code memory 201.

Note that the key code memory 201 and key press state memory 204
The signals are stored by selecting portions corresponding to each channel in a time-division manner in synchronization with each other.

Next, the key code tone high voltage conversion section 400 includes a sampling circuit 401, a sampling control circuit 402 that controls the sampling period, and a digital-to-analog conversion circuit 40.
3.

The key code pitch voltage converter 400 samples the key code KC supplied from the key assigner 300 in the sampling circuit 401 and supplies the sampled key code KC' to the digital-to-analog converter circuit 403.

In this case, the sampling period of the sampling circuit 401 is determined by the output of the sampling control circuit 402, and the period is the time when the clock for shifting the contents of the key code memory 201 is counted one more than the number of channels. ing.

Therefore, the sampling circuit 401 sequentially samples the key codes KC corresponding to different channels almost every time the key code memory 201 is shifted once, and continues to output the sampled key codes KC' until the next sampling time. Therefore, deceleration sampling is performed.

This is because the above-mentioned key coder 100 and channel processor 200 need to quickly detect the states of the key switches 101a to 101n (key pressed state and key released state) and assign them to channels; The parts that are handled do not require high-speed operation because they are processed in parallel, and the operation cannot keep up with the high-speed voltage of the analog signal.

That is, the waveform becomes dull due to minute capacitance in the circuit system and wiring system, and as a result, it becomes impossible to obtain an accurate musical tone that matches the key code KC.

For these various reasons, the key code KC is decelerated sampled to form the decelerated sampled key code KC'.

The digital-to-analog conversion circuit 403 connected to the output side of the sampling circuit 401 generates the above-mentioned key code KC'.
This is the part that converts the voltage into the corresponding pitch voltage KV.

This digital-to-analog conversion circuit 403 inputs the key code KC' decelerated and sampled by the sampling circuit 401 as described above, divides this key code KC' into a block code BC' and a note code NC', and decodes each. do.

Then, a voltage signal corresponding to the block is extracted from the resistor voltage divider circuit according to the decoded output of the block code BC', and this extracted voltage signal is converted into the note code N
By further dividing the voltage corresponding to the note using the decoded output of C', a tone pitch voltage KV corresponding to the key code KC' is generated.

This sound pitch voltage KV is controlled by the sampling circuit 401 by a control signal supplied from the sampling control circuit 402.
Each sampled key code KC' is distributed to the same channel to which it is assigned.

In this case, the operation of distributing the pitch voltage KV to each channel operates in synchronization with the key depression state memory 204 described above, and the selected channels also match.

In this way, the tone pitch voltage KV converted to the analog voltage corresponding to the key code KC' is distributed to each channel, but when converting the key code KC' to the tone pitch voltage KV, the digital Due to the minute capacitance of the circuit system in the loop-to-analog conversion section, some smearing occurs at the rising edge of the converted tone pitch voltage KV.

Therefore, when the tone pitch voltage KV converted corresponding to the key code KC' is supplied from the first part, that is, the rising start part, to the subsequent musical tone forming circuit, this pitch voltage K
A musical tone completely different from the key code KC' is generated in the accented portion of the rising portion of the V, and the frequency of this musical tone gradually increases to generate a musical tone with a frequency corresponding to the target key code KC'.

In this case, although the above-mentioned rounding occurs at the rise of the pitch voltage KV for a very short period of time, the musical tone at the start of sound generation is also important in musical instruments.

For this purpose, the above-mentioned digital-to-analog conversion circuit 40
3 is configured to distribute the tone pitch voltage KV to each channel only after the digital-to-analog conversion has been completed.

In other words, from the sampling circuit 401, the key code KC'
is supplied for a short period of time (1/n of the sampling output
), and then the tone high voltage KV is distributed to each channel.

Next, the sound generation series switching unit 500 switches and sets to which sound generation channel among the sound generation channels the tone pitch voltage KV outputted in parallel from the digital-to-analog conversion circuit 403 in accordance with the time of each channel is supplied. 1st to do
Select switch 501 and channel processor 20
a second select switch 5 for switching and setting which of the respective sound generation channels the key-on signal KO sent from the key press state memory 204 of 0 is to be supplied;
02, a third select switch 503 that switches and supplies musical tone control signals TM stored in advance for each tone generation series in the musical tone control signal memory 700 to each tone generation channel, and the states of the first to third select switches 501 to 503. The first to third selection switches 501 to 503 are driven in conjunction with the operation of the switch control part 504 to control the first to third select switches 501 to 503.
A tone pitch voltage KV, a key-on signal KO, and a musical tone control signal TM are supplied to each sound generation channel set by the third select switches 501 to 503, respectively.

Next, the musical tone forming section 600 has musical tone forming circuits 601a to 601h provided corresponding to each sound generation channel.

In this embodiment, the tone forming circuits 601a to 601h are voltage controlled variable frequency oscillators (hereinafter referred to as ``CO'').

) Voltage controlled variable filter (hereinafter referred to as VCF).

) and a voltage-controlled variable gain amplifier (hereinafter referred to as VCA).

) and an envelope generator EG that programs the control timing and control amount of each section VCO, VCF, and VCA. Then, the CO oscillates at a frequency corresponding to the input sound high voltage KV.

This oscillation output is sent out as a musical tone signal via the VCF and VCA, and the mixing resistors 900a to 900h
After being mixed with musical tone signals sent out from musical tone forming circuits in charge of other channels, the signal is supplied to a speaker (not shown) via an output terminal 901.

In this case, by controlling the VCO, VCF, and VCA with a control waveform signal generated from the envelope generator EG, the oscillation frequency of the VCO changes slightly according to this control waveform signal, and the frequency characteristics of the VCF change. The VCA generates a musical tone signal rich in naturalness and musicality, and furthermore, the VCA controls the musical tone envelope according to the control waveform.

A musical tone control signal TM sent from the musical tone control signal memory 700 is coupled to each envelope generator EG via a third select switch 503, and generates a control waveform signal having a waveform shape corresponding to the musical tone control signal TM. The generation timing of the control waveform signal is determined by the key-on signal K supplied from the key press state memory 204 of the channel processor 200 via the second select switch 502.
Controlled by O.

The timing signal generator 800 receives a reference clock signal (system clock) supplied from a reference oscillator (not shown).
is counted to generate various synchronization signals, and these synchronization signals are supplied to each of the above-mentioned parts to obtain overall operational synchronization.

The above description is an explanation of the main structure and operation of the main part of the block diagram schematically showing the overall structure (FIG. 1) showing one embodiment of the electronic musical instrument according to the present invention.

Hereinafter, the configuration and operation will be explained in detail using a diagram showing each block shown in FIG. 1 as a concrete circuit and an operation waveform diagram of the main part.

Before entering into the description of the concrete circuit, the special use of symbols in the circuit will be explained.

Figure 2 a % f shows an example of the symbols used. Figure 2 a shows an inverter, Figures b and c show an AND gate,
d and e in the same figure represent an OR gate, and f in the same figure represents a delay flip-flop, respectively.

In this case, in the above AND gate or OR gate, when the number of inputs is small, the normal display method as shown in bd of the same figure is adopted, and when the number of inputs is large, the normal display method as shown in c,
The special projection method shown in e is adopted.

In Figures c and e, one input line is drawn on the input side of the circuit, multiple signal lines are crossed with this input line, and the signal line of the signal to be input to the circuit and the input line are crossed. The points are circled.

Therefore, in the case of example C in the same figure, the logical formula is Q=A-B・
D, and the logical formula in the case of the example shown in the figure e is Q=A+B+C.

FIG. 3 is a specific circuit diagram showing a main part of the timing generating section 800 shown in FIG. 1, which is a part that generates a control signal that serves as a reference for the operation of this electronic musical instrument.

Therefore, this timing generating section 800 will be explained first.

This timing generating section 800 includes a 4-bit counter 801 composed of four flip-flops connected in cascade, and bits corresponding to the number of channels (in this embodiment, the circuit will be described below as having an 8-channel configuration).

) and a shift register 802.

The counter 801 is an output pulse Φ of a reference oscillator (not shown).
Of the output pulses Φ1 and Φ2 whose frequency is divided by two, the clock pulse Φ1 shown in FIG. 4a is counted as an input.

The pulse interval of this clock pulse Φ1 is, for example, an extremely high-speed pulse of 1 μs, and this pulse interval will hereinafter be referred to as "channel time".

Assuming that the number of simultaneous sounds in this electronic musical instrument is 8, the total number of channels is 8, and time slots of 1 μs width successively separated by clock pulse Φ1 are driven corresponding to channels 1 to 8 in sequence.

This is because the channel processor 200 described above has a dynamic logical configuration in which various storage circuits and logic circuits are shared in a time-sharing manner in order to be able to simultaneously generate a plurality of musical tones.

Furthermore, the above-mentioned channel times are generated in cycles every 8 channel times, if each time slot is designated as the 1st channel time to the 8th channel time in order, as shown in FIG. 4b. Become.

In other words, the clock pulse Φ is applied to the input terminal of the counter 801.
When 1 is supplied from an oscillator (not shown), this counter 801 sequentially counts the clock pulses Φ1 and outputs the count result as a pinary decimal code having a parallel 4-bit configuration.

Among these outputs, the output of the topmost flip-flop is
As shown in FIG. 4C, the first
It is taken out as pulses 81-S8 which send out an output over the range of channel time to eighth channel time.

Further, from the topmost flip-flop, as shown in FIG. 4d, ladles S, -S16, which are inverted versions of Hals 81-S8, are taken out.

Further, the parallel 4-bit output signal outputted from the counter 801 is determined to match in the AND gate 804, so that a full count state is detected, and the output at the time of this full count is converted into a pulse S, 6 as shown in FIG. 4e.
This pulse S16 is also output to the inverter 8.
05, a pulse S16 is obtained as shown in FIG. 4f.

In other words, this pulse S,6 is generated by the channel processor 20
This is generated every time (16 μS) for one allocation processing operation in 0, and requires the time for each channel time to cycle twice.

This is because the channel processor 200 compares the input key code KC with the stored key code KC, which has already been assigned, in the first 8 channel times, and then performs the writing process in the following 8 channel times. The pulses S1 to S8 and the pulses S to S16 shown in FIGS. 4c and d described above separate the first half of the 8-channel time and the second half of the 8-channel time.

In addition, the AND gate 806 determines the coincidence of the first to third outputs of the parallel 4-bit outputs output from the counter 801, so that
As shown in FIG. 3, pulses S8 and S16 are obtained which generate outputs at the time of the 8th channel.

Pulses S8, S sent out from this AND gate 806
16 is supplied to an 8-bit shift register 802 and sequentially shifted up, and from the output end of each bit,
As shown in ~Q, pulses BT1 to BT8 are obtained by sequentially sampling the first to eighth channel times.

Therefore, each bit output of the shift register 802 corresponds to the timing signals corresponding to the first to eighth channel times taken out in parallel.

Further, the first to seventh bit outputs of the shift register 802 are taken out via an OR gate 807, and an AND gate 4808 determines the coincidence between the output of this OR gate 807 and the most significant bit output of the counter 801. A clock pulse ΦA shown in FIG. 4h is obtained.

Further, the AND gate 809 obtains the clock pulse ΦB shown in FIG. 4I by determining the coincidence between the output of the OR gate 807 and the output of the inverter 803d.

The operations of each part are executed using such pulse signals and clock pulses as timing signals.

Hereinafter, the operation of each part will be explained in detail for each block using the above-mentioned timing signals.

Regarding the key coder 100, the present applicant has previously filed Japanese Patent Application No. 1983-100879 (Japanese Patent Laid-Open No. 52-23324) with the title of the invention "Key Coder". No. (Japanese Unexamined Patent Publication No. 52-24518) / Title of the invention "Key switch detection processing device" or Patent Application No. 75065 (Sho 51-75065) (Unexamined Japanese Patent Application No. 53-1014)
- Since the invention is described in detail in the specification of the title "electronic musical instrument," the explanation will be omitted here.

Channel Processor 200 First, the configuration and operation of the channel processor 200 will be described in detail.

5 to 8 show the key code memory 201 and key-on/off detection circuit 2 that constitute the channel processor 200.
02, truncate circuit 203 and key press state memory 2
FIG. 2 is a circuit diagram showing a specific example of No. 04.

The key code memory 201 shown in FIG.
Shift register register 20 for each bit KN1 to KN3 of C
5a to 205g, and this shift register 20
The number of stages (number of storage positions) from 53 to 205g corresponds to the number of musical tones that can be produced simultaneously, that is, the number of channels (in this embodiment, 8 channels as described above).

The shift registers 205a to 205g are driven by a two-phase clock pulse consisting of a clock pulse φ1 shown in FIG.
The output signal output from the final stage is output from each AND gate 206.
It is adapted to be fed back to each input side of each shift register 205a to 205g via a to 206g and each OR gate 207a to 207g.

Therefore, the shift registers 205a to 205g have a total of 8 stages capable of storing the key code KC having a parallel bit configuration by the number of channels.
This constitutes a stage 7-bit circular shift register.

Further, a key code KC constituted by bits l-KN1 to KB3 is supplied to the input side of each of the shift registers 205a to 205g via each AND gate 208a to 208g and each OR gate 207a to 207g.

Therefore, when a set signal is supplied to the line 209 from a key-on/off detection circuit 202, which will be described later, each AND gate 208a to 208g is opened, each bit signal KN1 to KB3 of the key code KC is taken in, and each shift register 205a -205g are all written and stored in the stage portion corresponding to the channel to which the key code KC has not yet been assigned.

The clock pulse φ1 determines which channel the stored key code KC (KN1 to KB3) is assigned to.
, φ2, each shift register 205a-2 is driven by
This can be determined based on the output timing of 05g.

This is because the clock pulses .phi.1 and .phi.2 and the channels to which the time-division allocation process is performed are synchronized and correspond to each other.

Therefore, the memory key code KC assigned to each channel is sequentially and time-divisionally output to the output terminals 210a to 210g for each channel time shown in FIG. will be returned and their memories will continue to be preserved.

In addition, the initial clear signal I is applied to the OR gate 207g.
C is supplied and a "1" signal is forcibly written at that timing.

Next, the key-on/off detection circuit 202 shown in FIG.
It has a key code comparison circuit 211, and each shift register 205a to 205g of the key code memory 201.
Memory key code KC and key coder 100 output from
A comparison has been made with the key code KC currently supplied by KC.

In this case, the stored key codes KC corresponding to each channel supplied to the key code comparison circuit 211 are supplied in circulation twice during one allocated time TP shown in FIG. 4b.

In other words, each channel time from the first to the eighth channels goes through one cycle in the first half assignment period TP1 (FIG. 4), and goes through another cycle in the second half assignment time TP2 (FIG. 4).

On the other hand, since the key code KC output from the sample hold circuit 106 of the key coder 100 is read out by the clock pulse φB shown in FIG.
The contents of this key code KC do not change during one allocation period TP.

Therefore, in a circuit configured in this way, 1
Within the allocation period TP, each shift register 2058~
By circulating the contents of 205g twice and outputting it, the first half of the period is TP, and the current key coder 100 is
A comparison operation is performed to determine whether or not the key code KC output from
In this step, an allocation operation is performed based on the first half comparison result.

Further, the match detection signal EQ output from the key code comparison circuit 211 is "1" if a match is obtained as a result of the comparison, and "0" if there is no match.

Whether the detected key code KC matches the key code KC assigned to which channel is determined based on the channel time when the match detection signal EQ becomes "1".

Then, for example, at the end of the first half assignment period TP1, the key code comparison circuit 211 outputs a "0" signal (indicating that the input key code KC has not been assigned to any channel yet) as the match detection signal EQ. Accordingly, the output of the AND gate 212 also becomes "0".

As a result, the "0" output signal of AND gate 212 is stored in delay flip-flop 215 via OR gate 213 and AND gate 214.

In this case, since the pulse S16 shown in FIG. 4f is supplied to one input terminal of the AND gate 214, the memory contents of the delay flip-flop 215 are held until the end of one allocation period TP.

The output signal of this delay flip-flop 215 is
O" is inverted in an inverter 216 and then supplied to an AND gate 217.

In this case, the number of storage stages (8 stages in this embodiment) corresponds to the number of channels, and the clock pulse φ1
, φ2 is provided, and the shift register 218 is driven in synchronization with the time of each channel, and the assignment status of each channel is written in this shift register 218 as a blank channel "0" and an assigned channel "1". They are being shifted sequentially.

Therefore, a blank channel is designated by determining the output of the shift register 218 and by the channel time at which the "0" output occurs.

In the second half allocation period TP2, the shift register 218
When a ``0'' output indicating a blank channel is generated from
``The ON signal is passed through the inverter 219 to the AND gate 2.
17.

In this case, the other three input terminals of the AND gate 217 include the "11" signal and the "4th" signal supplied via the inverter 216.
Since the "1" signal from the OR gate 220 that detects that the pulses S9 to S16 and the key code KC shown in FIG. AND gate 217 every time a “0” signal is output.
The output becomes "1", and this "1" signal is supplied to line 209 of key code memory 201 as a set signal.

When this set signal is supplied, the key code memory 20
1 stores the input key code KC in the stage corresponding to the blank channel as described above.

In this case, the shift register 218 inputs the same input key code KC to each stage corresponding to the blank channel of the key code memory 201 in order to output a "0" signal to all the blank channels at the corresponding channel time. will be written.

The AND gate (FIG. 6) uses the gate input of the AND gate 217 and the truncate signal as gate inputs.

As will be described later, this truncate signal is generated at the channel time corresponding to the oldest channel by determining the channel for which the key was released the earliest, and in particular, only one signal is generated at the corresponding channel time in the second half allocation period TP2. It is supposed to be done.

Therefore, from the AND gate 221, the set signal sent from the AND gate 217 outputs "1" at the channel time corresponding to the channel whose key was released earliest among the channels corresponding to the stages in which the input key code KC was written. A signal is output.

The "1" output signal of the AND gate 221 is a set signal output from the corresponding stage of the shift register 218, that is, the AND gate 217 via the OR gate 222, and the input key code KC is the set signal output from the first key code memory 217.
A "1" signal indicating that the allocation has already been completed to the storage stage of the shift register 218 which corresponds to the channel written to the stage written as "1" and which corresponds to the oldest key-released channel specified by the truncate signal. is written.

Next, input key code KC is already in key code memory 2.
01 and the allocation to a certain channel has been completed.

If the input key code KC has already been assigned to a certain channel, the match detection signal EQ of the key code comparison circuit 211 becomes "1".

This coincidence detection signal EQ=″′ is generated by the AND gate 212
supplied to

The input of this AND gate 212 is the shift register 218
All outputs are "1" except for the output of.

Therefore, at the timing when the coincidence detection signal EQ is "1" and the output signal of the shift register 218 is ffig, the AND gate 212 satisfies the conditions and outputs a "1" signal.

This "1" signal is supplied to the delay flip-flop 215 via the OR gate 213 and the AND gate 214, and is supplied to the delay flip-flop 215 for one allocation period TP (FIG. 4) as in the case described above.
It is retained until the end of .

However, an inverter 216 is provided on the output side of the delay flip-flop 215, and when the key code comparison circuit 211 outputs the match detection signal EQ="l", the AND gate 217 and the AND gate 2
No "1" signal can be obtained from 21 and no allocation operation is performed.

The above operation is the channel assignment operation of the input key code KC in the key-on/off detection circuit 202.

Next, the key release detection operation of the key-on/off detection circuit 202 will be explained.

In the channel assignment operation described above, the tend gate 221 outputs a "1" signal at the channel time corresponding to the channel to which the assignment has been executed, and the assignment of this channel to the stage corresponding to that channel of the shift register 218 is completed. A “1” signal indicating that the device is present is written.

Therefore, this shift register 218 stores the allocation state of each channel, and the information stored in this shift register 218 is sequentially shifted by clock pulses φ1 and φ2 corresponding to the channel time, and is sequentially shifted from the last stage. The signal is output and supplied to a key press state memory 204, which will be described next, and is also applied to the input side via an AND gate 223 and an OR gate 222, thereby being sequentially circulated and stored.

On the other hand, a signal indicating the assigned channel outputted from the AND gate 221 is sequentially written and stored in an 8-stage shift register 225 having the same configuration as the shift register 218 via the OR gate 224.

Therefore, at this point, the shift register 225
The contents of are the same as the contents of the shift register 218, and are sequentially shifted by the same clock pulses φ1 and φ2.

The signal output from the final stage of the shift register 225 is returned to its input side via the AND gate 226 and held there.

The start signal X sent from the key coder 100 described above in the fourth state (standby state) is passed through the inverter 227 to the AND gate 226 . and inhibits AND gate 226, thereby resetting all contents of shift register 225.

After this reset operation is completed, the shift register 225
is the output signal of AND gate 221 and AND gate 2
The output signal of AND gate 212 is written through 28.

By performing such an operation, a "1" signal is written in the shift register 225 to the stage corresponding to the channel to which the key switch being operated after the fourth state (standby state) is assigned. Self-holding until the next start signal X is generated.

On the other hand, since the shift register 218 does not perform any reset operation, it continues to store a "1" signal in the corresponding stage even for channels whose keys are subsequently released.

In this case, when the fourth state is entered again and the start signal X is supplied, the output signal of the shift register 225 is no longer fed back to the input side, but is supplied to the NAND gate 230 via the inverter 229.

This NAND gate 230 receives pulse signals 81 to S8 shown in FIG.
The inverted output signal of the shift register 218 and the output signal of the shift register 218 are supplied.

Therefore, in the fourth state and the pulse signals 81 to S
The outputs of the shift register 218 and the shift register 225 are compared only in the period No. 8 (first half allocation period TP1).

When the output of the shift register 218 is "1" and the output of the shift register 225 is "0", that is, after the latest fourth stay state, the key code KC assigned to that channel is the same as the key code KC assigned to that channel. When the key code KC is not continuously supplied (that is, the key is released), the output of the inverter 229 becomes "1", so the output of the NAND gate 230 becomes "0", indicating that the key is released. Discover channels.

Therefore, this NAND gate 230 outputs "
By determining the channel time of the 0" signal, it can be determined which channel the key was released on.

This ``0'' output signal of the NAND gate 230 inhibits the AND gate 223, so that the ``1'' output signal of the shift register 218 is no longer returned to the input side, which corresponds to the channel whose key has already been released. The stage "1" signal is forcibly rewritten to a "0" signal.

Note that 231 is an inverter that supplies a "1" signal, which is an inversion of the "0" signal output from the NAND gate 230 indicating that a key release channel has been detected, to the truncate circuit 203, which will be described below; and 232 and 233, which will be described later. The shift register 218 is controlled by the enable signal INB.
, 225 to forcibly write a "1" signal.

Next, the truncate circuit 203 will be explained.

FIG. 7 shows a specific embodiment of the track skate circuit 203, and shows the key-on/off detection circuit 20 described above.
When the key released channel is detected from the NAND gate 230 of No. 2, this key release channel detection signal is inverted to a "1" signal by the inverter 231 and sent to the OR gate 23.
4 and stored in delay flip-flop 235.

The output signal of delay flip-flop 235 is returned to the input side via AND gate 236 and OR gate 234 and held there.

In this case, the other input of the AND gate 236 is as shown in FIG.
Since the pulse signal S16 shown in FIG. 2 is supplied, the contents of the delay flip-flop 235 are held until the end of the allocation period TP and then reset.

In this state, when the output is sent from the shift register 218 of the key-on/off detection circuit 202, the "1" signal is supplied from the inverter 237 at the channel time corresponding to the unallocated channel, so During the allocation period TP2 (pulses S9 to S16), the signal from the AND gate 238 to the shift register 218 is
A pulse signal is sent out in response to the "O" output.

Note that, as will be explained later, the output of the NAND gate 239 and the enable signal INB are "1" in this case.

The output signal of this AND gate 238 is supplied to the input terminal CI of the adder 240, thereby input terminals A1 to
"1" is added to the 3-bit augend signal supplied to A3, and this addition result is output as a 3-bit signal to the output terminal S.
1 to S3.

In this case, the output terminals 81 to S3 of the adder 240 are connected to AND gates 241a to 241c, each of which uses the output of the inverter 237 as one input signal, and the inverter 237 outputs a "1" signal. AND gates 241a to 24 only when the channel time corresponds to a channel to which no allocation has been made.
1c is opened and OR gate 242 and AND gate 2
Shift registers 245a to 24 through 43 and 244
5c, respectively.

Note that the AND gates 243 and 244 are connected to the inverter 24
6 (in this case, the initial clear signal IC is not generated).

The shift registers 245a to 245c are constituted by a shift register having storage stages corresponding to the number of channels (8 stages in this embodiment), and are sequentially shifted by clock pulses φ1 and φ2 synchronized with the channel time and output from the final stage. A signal is being sent.

Each output signal of the shift registers 245a to 245c is transmitted to each input terminal A for the augend signal of the adder 240 described above.
1 to A3, respectively.

Therefore, these parts are connected to the key-on/off detection circuit 2.
02 detects the aforementioned key release, each shift register 2
Among the stages 45a to 245c, in the stage corresponding to the blank channel of the shift register 218,
This constitutes a key release channel progress storage circuit 247 that sequentially adds 1 to the current count value.

Since this key release channel progress storage circuit 247 uses shift registers 245a to 245c having an 8-stage configuration in a 3-stage parallel configuration, the key release progress signal of parallel 3 bits given to each channel is stored in channel time. The key release progress signal having the largest value is output as a 3-bit signal (pinary code) at the channel time corresponding to the oldest key release channel.

In this case, since the key release channel progress recording failure circuit 247 has a 3-bit configuration as described above, the maximum output value thereof is 7 ("111"), and when 1 is added to this, O( ``000''), and the oldest key-released channel becomes the latest key-released channel.

For this purpose, the output side of each shift register 245a to 245c is equipped with a NAND gate 2 for matching 3-bit signals.
39 is provided, and by inhibiting AND gate 238 by the output signal of NAND gate 239, subsequent addition is stopped in that channel, thereby eliminating the above-mentioned disadvantage.

By performing the above-described operation, it is possible to sequentially allocate channels starting from the earliest key release using the circuit described below.

This is because sustain is added after a key is released, so if many keys have been operated, it is necessary to determine the oldest key release channel and assign a new key code.

A 3-bit key release progress signal output from the key release channel progress storage circuit 247 corresponding to each channel time is supplied to delay flip-flops 250a to 250c via AND games h248a to 248c and OR gates 249a to 249c for each bit. It is designed to be recorded and memorized.

In this case, each delay flip-flop 250a-250c
Since the 3-bit signal stored in the 3-bit signal is read in with clock pulse φ1 and read out with clock pulse φ2, it is output after being delayed by one clock pulse, and each output signal is output from each AND gate. 251a~
251c and each OR gate 249a to 249c, it is returned to the input side and stored therein.

Therefore, delay flip-flops 250a-250c
constitutes a memory circuit that stores a 3-bit signal.

The output signals of delay flip-flops 2503-250c are supplied to comparator 252 as a 3-bit key release progress signal.

Comparator 252 includes delay flip-flops 250a-25.
Compares the key release progress signal B delayed by one clock time supplied from 0c with the new key release progress signal A supplied from the key release channel progress memory circuit 247, and outputs "1" only if A>H. is configured to occur.

The "1" signal output from this comparator 252 is transmitted to each AND gate 241a to 241c via a NOR gate 253.
is supplied as a '0'' signal to the delay flip-flops 250a-250c, thereby preventing the output of each delay flip-flop 250a-250c from returning to the input side.

Moreover, the "1" signal output from this comparator 252 is
Since this AND gate 254 is supplied to the comparator 25 in the first half allocation period TP1,
The AND condition is satisfied at the output sending timing of 2,
As a result of the output, each bit signal of the new key release progress signal A from the memory circuit 247 is transmitted to the AND gates 248a to 248.
c to delay flip-flops 250a-250c.

Therefore, these are the closest key release progress signal extraction circuit 25 that extracts the shortest key release progress signal from among the key release progress signals of each channel.
At the end of the first half allocation period TP, only the most recent key release progress signal is stored in the delay flip-flops 250a to 250c, and the pulse signal S16 (
It is reset at the end of one allocation period TP according to FIG. 4e).

Further, the output signal of the AND gate 254 generated in the first half allocation period TP1 is
256c, and at this timing, the output from the timing signal generator 800 shown in FIG.
A signal in which each channel of bits is coded, that is, channel code signals HC1 to HC3 (channel time converted into a pinary code) is sent to each OR gate 257a.
~257c, each delay flip-flop 258a
~258c, respectively.

The delay flip-flops 258a to 258c
As in the case of the most recent key release elapsed signal extraction circuit 255, since the output signal of the NOR gate 253 is supplied to the AND gates 259a to 259c, the contents of Channel code signals HC1-HC3 representing the channel on which the signal occurs will be stored.

The channel code signals HC1 to HC3 representing the channels in which the most recent key release elapsed signals stored in the delay flip-flops 258a to 258c are generated are stored in the respective delay flip-flops 258a to 258c.
It is held until the end of P (FIG. 4).

Pulse signal S16 supplied via NOR gate 253
It is reset by (Fig. 4e).

The channel code signals HC, -HC3 stored in the delay flip-flops 258a-258c are supplied to a comparator 260 to determine whether they match the input channel code signals HC1-HC3.

When both signals match, a match signal "1" is output at that timing and supplied to the AND gate 221 of the key-on/off detection circuit 202 as a truncate signal.

In this case, since channel code signals HC1 to HC3 circulate twice during one allocation period TP (Fig. 4),
Since writing is performed to each of the delay flip-flops 258a to 258c during the first cycle period (first half allocation period TP1), the coincidence output signal from the comparator 260 is generated only once in a certain channel time during the second half allocation period TP2. It will be output.

Therefore, these circuits constitute the oldest key release channel extracting circuit 261, which corresponds to the oldest key release channel (the channel in which truncation has progressed most) in the second half allocation period TP2 of each allocation period. A pulse signal as a truncate signal is output at the channel time when the key on/off detection circuit 202 is assigned a new key code KC.
It is specified exactly once.

Note that in the key release channel progress recording/disabling circuit 247, writing the initial clear signal IC only to the shift register 245a via the OR gate 242 is done by first writing a "1" signal to all stages of the shift register 245a to obtain the initial state. This is to ensure the truncation operation in .

In other words, when the contents of the shift registers 245a to 245c are all reset, the comparator 252 in the closest key release elapsed signal extraction circuit 255 cannot obtain the "1" signal that is output when A>B. Put it away.

As a result, the channel code signals HC1 to HC3 are no longer stored in the delay flip-flops 258a to 258c of the earliest key release channel extraction circuit 261, and the delay flip-flops 258a to 258c are reset by the pulse signal supplied via the NOR gate 253. continue in the same state.

As a result, the condition A=B cannot be obtained in the comparator 260, a truncate signal is not generated, and the first generated key code KC is not assigned.

In order to solve this problem, the initial clear signal IC is used to forcefully write a "1" signal to all stages of the shift register 245a.

Therefore, "1" by this initial clear signal IC.
″Writing of the signal is not necessarily done in the shift register 245a.
The shift register 2 with a three-stage configuration is not limited to
It is sufficient if it is configured to forcibly write a "1" signal into at least one of 45a to 245c.

The above description is the operation of the truncation circuit 203 that specifies only one channel that has been truncated the most.

Next, the key press state memory 204 will be explained in detail.

FIG. 8 shows a specific embodiment of the key press state memory 204, in which output signals from the shift register 218 of the key-on/off detection circuit 202 described above are sequentially supplied to each AND game 262a to 262h. ing.

In this shift register 218, as described above, a "1" signal is written only in the stage corresponding to the channel to which the key code KC is assigned, and a "0" signal is written in the stage corresponding to the channel to which the key is released. It has been rewritten as ``.

Therefore, the signals sent from the shift register 218 in a time-division manner corresponding to each channel time represent the current key depression state of the key assigned to each channel.

This state is memorized and the clock pulses φ1, φ2
Shift register 2 is sent out while being sequentially shifted in
When the output signal No. 18 is supplied to the key pressed state memory 204, the output signal is in the "'1" state, that is, during the channel time when the key corresponding to the assigned key code KC is pressed, as shown in FIG. Timing signal generator 80 shown in
AND gates 262a to 262a of the portions where the timings of channel signals BT1 to BT8, which are sequentially output in a time-division manner from 0 to each channel (corresponding to channel time) in a time-divisional manner as shown in j=Q in FIG. The condition of 262h is satisfied, and the "1" output is the OR gate 263a to 263h.
are stored in delay flip-flops 264a to 264h via AND gates 265a to 265h and OR gates 263a to 263h, and held by their outputs being returned to the input side via AND gates 265a to 265h and OR gates 263a to 263h.

Therefore, the first key is
~ Delay flip-flop 26 responsible for the 8th channel
Only for the corresponding channel section from 4a to 264h"
1" signal is stored, and the next corresponding channel signal BT1 to BT8 generated in a time-division manner is transmitted to the inverter 266a.
It will continue to be held until AND gates 265a to 265h are inhibited via 266h.

For example, when a "1" signal is output from the shift register 218 (FIG. 6) at the third channel time shown in FIG. 4, the channel signal generated at this third channel time will be as shown in FIG. There is only channel signal BT3.

As a result, the condition is satisfied only in AND gate 262c, and its output signal is written to delay shift register 264c via OR gate 263c.

These circuit parts constitute a serial-parallel conversion circuit 267 that converts a signal representing the key press channel of the shift register 218, which is serially output in a time-division manner corresponding to the channel time, into an 8-channel parallel signal. There will be.

Therefore, each of the delay flipflops 264a to 264h of this serial/parallel conversion circuit 267 is sequentially written with the output signal of the shift register 218 (FIG. 6) indicating the key depression state of the channel by the channel signals BT1 to BT8.

From this serial/parallel conversion circuit 267, output lines 268a to 268 corresponding to each channel are connected.
h, a "1" signal is output only to the channel to which the key code KC is assigned and to which the key corresponding to the key code KC is pressed.

For example, as described above, in the third channel, if a key is pressed, a "1" signal is output to line 268c.

In this way, "1" is output corresponding to the key pressed channel.
“The signal is supplied to the gate electrodes of the field effect transistors 270a to 270h via the NOR gates 269a to 269h, and turns off the field effect transistors to connect the input/output transistors provided corresponding to the first to eighth channels. A "1" signal is sent to the dual-purpose terminals 271a to 271h.

For example, as described above, if the third channel is designated, then the delay flip-flop 264c to the line 26
A "1" signal is supplied to the NOR gate 269c via the NOR gate 269c, and only the transistor 270c is turned off by the "0" output signal of the NOR gate 269c.

As a result, only the input/output terminal 271c becomes "1".
and other input/output terminals 271a, 271b, 271d.
~271h becomes "0".

Therefore, among the input/output terminals 271a to 271h, a portion where a "1" signal is sent indicates that a key is pressed in the corresponding channel.

This "1" signal, that is, the key-on signal KO, is transmitted to the corresponding musical tone forming circuit 60 of the musical tone forming section 600, which will be described later.
1a to 601h are controlled.

The key depression state memory 204 is also provided with a mode terminal 272 for switching the number of sound generation channels.

This switching of the number of sound generation channels is necessary in the following cases.

For example, there are cases where it is desired to obtain a sound effect similar to when a piano and pipe organ are played together.

To accomplish this, a tone forming circuit for forming a tone of another tone is connected in parallel to the tone forming circuit of a certain channel.

In this case, it would be sufficient to arrange musical tone forming circuits in parallel for all channels, but providing a plurality of such circuits in parallel would significantly increase the cost.

For this purpose, the number of used channels is reduced, and the pitch voltage KV of the other channel is supplied to the musical tone forming circuit of the reduced channel, so that the same pitch voltage KV is supplied. It is conceivable to obtain different kinds of tones based on V.

Furthermore, when the channel processor 200 with a fixed number of channels is applied to a model with a small number of musical tone forming channels, the number of control channels in the channel processor 200 can be reduced and used in common.

In this case, since the channel processor 200 is integrated, the number of terminals is limited, and providing a plurality of terminals used only for switching the number of channels is disadvantageous when adding other functions.

Therefore, it is necessary to perform the above-described processing using at least one mode terminal for switching the number of channels.

The key press state memory 204 shown in FIG. 8 is provided with such a function.

That is, one side input terminal of the OR game 273b to 273h is connected to each of the input/output terminals 271b to 271h.

The other input terminals of the OR gates 273b to 273h are connected so as to be supplied with the output signals of adjacent lower order (in this case, the one with the highest channel number) OR games 273c to 273h.

Further, the output of each OR gate 273b to 273h is transmitted to a NOR gate 269a via an inverter 274b to 274h.
~269g is supplied to the input side.

In addition, a mode terminal 272 that performs control for switching the number of control channels is connected to one input terminal of the lowest OR gate 273h, and is connected via an inverter 2741 to a NOR gate 269h provided in the lowest channel.
It is one of the inputs.

In a circuit configured in this way, when all channels are operated independently, a "1" is input to the mode terminal 272.
supply the signal.

As a result, the "1" signal of the mode terminal 272 is passed through the inverter 2741, and its inverted signal "O" is output to the NOR gate 26.
A transistor 270h connected to the output of this NOR gate 269h to be supplied to 9h is placed under the control of a delay flip-flop 264h.

In addition, the other NOR gates 269g to 269a also receive the ``1'' signal supplied to the mode terminal 272 as an OR gate 273h.
Further inverters 274h to 274b via ~273b
Since the inverted "0" signal is supplied through All channels can be played.

Also, output signal A of inverters 274b to 2741.

-Timing signal generation circuit 80 with A7 as one input
0 (FIG. 3), the output signals of the AND gates 810a to 810h are always "0", and accordingly, the enable signal INB sent from the NAND gate 811 is "1" during the first to eighth channel periods. The various parts described above are controlled.

Next, for example, key codes KC are assigned to seven channels from the first to seventh channels to generate sounds, and musical tones of different tones are formed using the key code KC assigned to the eighth channel, for example, to the first channel. When generating a sound to obtain an ensemble effect, the following control is performed.

First, the musical tone forming circuit of the eighth channel is removed and connected in parallel with the musical tone forming circuit of the first channel.

Next, a "1" signal is supplied to the input/output terminal 271h of the eighth channel of the key press state memory 204, and a "0" signal is supplied to the mode terminal 272.

When such an operation is performed, the output signal of the inverter 2741 is inverted to "1" and the output signal of the NOR gate 269h becomes "O", so that the transistor 270h is turned off.

As a result, the output signal of the OR gate 273h becomes "1", and the output signal of the OR gate 273h is sequentially passed through the OR gates 273g to 273b to the inverters 274h to 2.
74b, the outputs of inverters 274b-274h are all "0", and all transistors 270a-270g except transistor 270h are placed under the control of delay flip-flops 264a-264g.

Also, only the output signal A7 of the inverter 2741 is “1”.
As a result, the enable signal INB output from the NOR gate 811 is satisfied because only the AND gate 810h of the timing signal generating section 800 in FIG. This is a signal generated during the period from channel signals BT1 to BT7.

When the enable signal INB becomes "0" at the 8th channel time, the output of the AND gate 212 of the key-on/off detection circuit 202 (FIG. 6) is forced to "0" at the 8th channel time. shall be.

In addition, the enable signal INB, which becomes n O M only in the 8th channel time, is controlled by the key-on/off detection circuit (
After being inverted via the inverters 232 and 233 of FIG. 6), the OR gate 222 and the OR gate 2
24 to the input sides of shift registers 218 and 225, respectively.

Therefore, at the 8th channel time, the inverted enable signal I becomes "0" at the 8th channel time.
NB forces a "1" signal to be written to the corresponding stage of the shift register 218225.

As a result, the eighth channel portion is in an allocated state, that is, in a state in which it is impossible to allocate the input key code KC.

Therefore, the key code KC for the 8th key is assigned to a channel other than the 8th channel by the above-mentioned truncation operation, and the assignment control of the key code KC to the 1st to 7th channels, which reduces the number of channels by one, is performed. will be carried out.

Next, when using the 1st to 6th channels, supply the n O M signal to the input/output terminal 271h and mode terminal 272 of the key press state memory 204 (Fig. Signal A is output from inverters 274b to 274g by supplying a "1" signal to 271g.

-A is set to "0", and signals A6 and A7 output from the inverters 274h and 274i are set to "1".

When only the signals A6 and A7 become "1", the AND gate 810g of the timing signal generation circuit 800 shown in FIG.
, 810h, the condition is satisfied during the seventh and eighth channel times, and the enable signal INB becomes "0" only after the seventh and eighth channel times from the NOR gate 811.
is output.

When the enable signal INB becomes n O 41 at the time of the 7th and 8th channels, "1" is placed in the stages corresponding to the 7th and 8th channels of the shift registers 218 and 225 (FIG. 6), as in the case described above. By forcibly writing a signal, the seventh and eighth channels are made unallocable, thereby changing the control of the circuit to the first to eighth channel configurations.

In addition, the enable signal INB, which becomes "'0" only during the channel time corresponding to the unused channel, is
AND gate 2 of truncate circuit 203 shown in FIG.
38, and this enable signal INB forcibly prevents monitoring of the key release progress for the channel corresponding to the channel time when nO41, and prevents generation of a truncate signal for this channel. ing.

Therefore, in the above explanation, the number of channels to be used can be selected sequentially from the higher ranked channels, and this selection is made only when the enable signal IN is applied during the channel time corresponding to the channel that is desired to be unused.
It is only necessary to control B to be ``0''.

For this purpose, the output signals A of the inverters 274b to 274h of the key press state memory 204 in charge of unused channels are used.

~Input/output terminal 271a so that A7 becomes ゛゜1゛.
~271h may be controlled appropriately, and the number of used channels and the above output signal A.

-A7 relationship is shown in Table 2.

In addition, the input/output/common terminal 27 of the key press state memory 204 is added to change the number of channels.
Control signals to 1a to 271h and mode terminal 272 are as shown in Table 3.

Therefore, as explained above, the key press state memory 20
4 converts the signal output from the shift register 218 of the key-on/off detection circuit 202 corresponding to the channel time of each channel into a parallel signal and supplies it to the corresponding channel, thereby converting the channel to which the key code KC is assigned. It has the function of operating only the channel whose key is pressed and the function of changing the number of assigned channels in response to the signals applied to the mode terminal 272 and the input/output terminals 271a to 271h. .

Key code/pitch voltage converter 400 Next, the key code/pitch voltage converter 400 will be explained in detail.

9 and 10 show the key code tone high voltage converter 40
This key code/pitch voltage conversion section 400 includes a sampling control circuit 402 shown in FIG. 9 and a sampling circuit 4 shown in FIG. 10.
01 and a digital-to-analog conversion circuit 403.

In this case, in the key code/pitch voltage conversion section 400, the sampling control circuit 402 that generates the reference timing signal and control signal will be explained first.

FIG. 9 shows a specific circuit diagram of the sampling control circuit 402, and the inverter 404 is supplied with an inverted signal BT8 of the channel signal BT8 output from the timing signal generator 800 shown in FIG. has been done.

Therefore, 8 driven by clock pulses φ1 and φ2
In the bit shift register 405, a "1" signal is written in the first stage by supplying the BT8 signal outputted from the inverter 404 via the OR gate 406, and is sequentially shifted using clock pulses φ1 and φ2.

Each stage of this shift register 405 outputs channel signals BT1 to BT8 (FIG. 18 b-h) that are the same as the channel signals BT1 to BT8 output in FIG. 3.

Then, when the one 4 "1" signal written in the first stage of this shift register 405 is shifted to the final stage, the output of the NOR gate 407 becomes "1" and the first stage becomes "1" again.
is written.

Therefore, shift register 405 is driven in synchronization with shift register 802 shown in FIG.

The reason why two shift registers are used and driven synchronously to obtain the same channel signals BT1 to BT8 is that when the circuit is divided into multiple blocks and integrated, or when both are placed in relatively separate parts. This is to easily obtain eight synchronized channel signals BT1 to BT8 by using only one synchronizing signal line, for example, in the case where the synchronizing signal line is provided in a single synchronizing signal line.

The first to third outputs of this shift register 405 are outputted via an OR gate 408 to a clock pulse φ shown in FIG. 11Q.
The fifth to seventh outputs are taken out as a clock pulse φA' shown in FIG. 11R via an OR gate 409.

The output signal BT8 of the inverter 404 is output from the OR gate 410.
It is also supplied to the input side of a 9-bit shift register 411 driven by clock pulses φ1 and φ2.

Therefore, from the final stage output of this shift register 411, clock pulses φ1 and φ2 are output as shown in FIG.
The pulse signal SC is output every ninth count.

Further, an inverted signal SC of the pulse signal SC shown in FIG. 11k is taken out from the inverter 412.

Furthermore, the output signals of the first and final stages of the shift register 411 are passed through a NOR gate 413 to form a pulse signal SOF which becomes "0" only when the 9th and 1st bits are output, as shown in FIG. 11n. It is outputting.

The above is the explanation of the sampling control circuit 402, and since the various pulse signals output here are used in the sampling circuit 401, which will be explained next, that part will be explained in detail.

FIG. 10 shows a specific embodiment of the sampling circuit 401 and the digital-to-analog conversion circuit 403, and the output key code KC of the key code memory 201 shown in FIG. 1 is supplied from the sampling control circuit 402. Each bit signal KN1 to KB3 is input to each AND gate 414a to 414 by a pulse signal SC (FIG. 11j).
g and OR gates 415a-415g to delay flip-flops 416a-416g for storage.

Then, the next pulse signal SC is supplied to the inverter 417, and this stored information (memory key code) is stored in each AND gate 418 by the "0" output of this inverter 417.
held until a~418g is inhibited.

In this case, since the shift register 411 in FIG. 9 has a 9-bit configuration, which has one stage more than the number of channels, as described above, the pulse signal SC output from the shift register 411 is transmitted for one cycle of the channel time. Each channel becomes a pulse signal synchronized with a different channel time.

Therefore, the pulse signal SC, which is the final stage output signal of this shift register 411, causes the key code memory 20 to
By sampling one 'output key code KC', key codes KC' of different channel times can be sequentially sampled.

In other words, as shown in FIG. 11J, the pulse signal S01 is sampled from the key code KC corresponding to the first channel signal BT, and then sent to the delay flip-flops 416a to 416.
The pulse signal SC2 generated in the next period can be stored in the delay flip-flops 416a to 416g by sampling the key code KC corresponding to the second channel time BT2.

Therefore, the sampling in this part is to slow down the output key code KC of the key code memory 201 to 1/8 and sample it sequentially for each channel, and this sampled key code KC' is The memory state continues to be held until sampling.

The reason for performing such deceleration sampling is that the digital-to-analog converter circuit 403, which will be explained next, cannot follow high-speed operation, and the subsequent circuit system performs parallel processing divided by channel, so time-division processing is performed. key coder 100 and channel processor 20
This is because high speed such as 0 etc. is not required.

Therefore, the sampling circuit 4 slows down these parts and sequentially captures the key code KC for each channel.
01.

Next, the key code KC' decelerated and sampled by the pulse signal SC of the sampling circuit 401 and stored in the delay flip-flops 416a to 416g is as follows.
Note code KN'~KN,' and block code KB1
'~KB3' and decoders 419 and 4, respectively.
20, where it is converted into a parallel decimal signal, and a "1" signal is output only to the output terminal corresponding to the code.

For example, the key code KC representing the B note of the 5th block.
When ' is supplied, "1011" is supplied to the input terminals A to D of the decoder 419, and "101" is supplied to the input terminals A to C of the decoder 420.

Therefore, the decoder 420 that converts the block codes KB1' to KB3' outputs a "1" signal only to the output terminal 5.

Also note code KNS ~ decoder 41 that converts phantoms
9, the "'1" signal is output only to the output terminal 13.

As a result, transistors 420a to 420l and 4
Among the transistors 21a to 421f, the transistor 420 is connected to the terminal 13 and the terminal 5 from which the output "1" signal is output.
Only transistor 421a and transistor 421a are turned on.

As a result, the potential at point A of the first voltage dividing circuit 422, which is configured to divide the voltage of the power supply 11 by the voltage dividing resistors r' to 16r', is connected to the plurality of resistors r and A second voltage divider circuit 4 configured by a resistor R
It is supplied to point a of 23.

On the other hand, when the transistor 420b is turned on by the output of the decoder 419 as described above, the potential at point b is taken out and output.

In this case, the potential at point a is block code KB'1 to KB
Since the output signal of the transistor 420b is the output of the first voltage dividing circuit 422 selected corresponding to S, the output signal of the transistor 420b corresponds to the block code KB1'~KB1 and the note code KNS~K.
A voltage value corresponding to N'4 is obtained, and this becomes a pitch voltage KV that controls a voltage-controlled variable frequency oscillator, which will be described later.

The key code KC supplied from the key assigner 300 is
Since the signal is decelerated sampled and supplied to the decoders 419 and 420, the output signal is held for one cycle of deceleration sampling, as shown in FIGS. 11d and 11m.

In this case, when converting a digital signal into an analog sound pitch voltage KV, transistors 420a to 420l, 421a to 42 connected to the output sides of decoders 419 and 420
Due to the capacitance at 1f etc. and the stray capacitance in the circuit system, the rising part of the converted output signal (pitch voltage KV) rises in accordance with the number of CR points, so some distortion occurs. This problem does not become a problem as it is processed at the time of allocating the pitch voltage KV to each channel, which will be explained next.

The pulse signal SC generated in the sampling control circuit 402 is also supplied to each AND gate 424a to 424h of the digital-to-analog conversion circuit 403.

The other input terminal of each AND gate 424a to 424h is connected to a channel signal B shown in FIG. 11 b to i.
Since T1 to BT8 are supplied, the pulse signal SC
Only the AND gate 424 to which the channel signal synchronized with the generation timing of FIG.
5h through delay flip-flops 426a-426
It is stored in h.

The pulse signal SC supplied to the AND gates 424a to 424h is supplied to the shift register 411 (which has counted one clock pulse more than the number of channels as described above).
Since it is the final stage output signal of FIG. 9), it matches the channel signals sequentially shifted by one with respect to channel signals BT1 to BT8.

Therefore, this pulse signal SC is the channel signal B
This means that T1 to BT8 are decelerated to 1/8 and sampled, and this sampled channel signal B
Any one of T1 to BT8' is stored in one of delay flip-flops 426a to 426g and continues to be held until AND gates 427a to 427h are inhibited by the output signal of inverter 417 when the next pulse signal SC is supplied. It will be done.

In this case, the deceleration sampling of the channel signals BT1 to BT8 and the key code KC is performed by the same signal, that is, the pulse signal SC, and the key code KC supplied to the key code/pitch voltage converter 400 is The key code is supplied at the channel time corresponding to the assigned channel.

As a result, the tone pitch voltage KV obtained by converting the key code KC' sampled by the sampling circuit 401 into an analog signal is taken in by the pulse signal SC and sent to the delay flip-flops 426a to 426h of the channel in which the "1" signal is stored and held. It would be a good idea to supply it to

Therefore, the delay flip-flops 426a-42
By turning on the transistors 428a to 428h connected to the output side with the output signal of 6h, the pitch voltage KV is transferred to the target channel (allocation processing is performed in the channel processor 200) via the output terminals 429a to 429h. It is possible to supply the pitch voltage KV only to the selected channels.

In this case, each delay flip-flop 426a-426h
AND gates 430a to 430h are provided on the output side, and each gate 430a to 430h is controlled by the pulse signal SOF shown in FIG. 11n output from the NOR gate 413 of the sampling control circuit 402 shown in FIG. has been done.

This pulse signal SOF is transmitted to the 9-bit shift register 411
Since the output of the first stage and the output part of the final stage are "1", the signal becomes "0" for two channel times from the generation of the pulse signal SC.

The pitch voltage KV output from this digital-to-analog conversion circuit 403 to each channel becomes a signal in which the time portion of the first two channels is inhibited, as shown in FIG. 11 o and p, and the rise of the pitch voltage KV The pitch voltage K is now in a stable state with the accent that sometimes occurs completely removed.
Only V is sent out.

The above explanation describes the sampling circuit 401 that decelerates and samples the key code KC supplied from the key assigner 300 and sequentially captures it for each channel, and the sampling circuit 401 that decelerates and samples the key code KC supplied from the key assigner 300 and sequentially captures it for each channel, and converts the sampled key code KC into a corresponding analog signal to generate a pitch voltage KV. This is a detailed explanation of the digital-to-analog converter circuit 403 that generates the tone pitch voltage KV and supplies this pitch voltage KV to the channel to which this key code KC' is assigned.

Pronunciation series switching unit 500 Next, the pronunciation series switching section 500 will be explained.

FIG. 12 shows a specific embodiment of the pronunciation sequence switching unit 500, in which the first to third select switches 501 to
503 and a switch control section 504.

As the first select switch 501, seven interlocking rotary type switches 501a to 501g each having four fixed contacts a=d are provided.

The movable contacts e of each of the switches 501a to 501g are connected to supply tone pitch voltage KV to each sound generation channel CH2 to CH8, which will be described in detail later, of the tone forming section 600, respectively.

When the movable contact e is located at the fixed contact a, the switches 501a to 501g have a pitch voltage of KV2 to KV2.
■8 is supplied to sound generation channels CH2 to CH8, respectively, and when movable contact e is located at fixed contact b, tone pitch voltage KV, is supplied to tone generation channels CH1, CH2, tone pitch voltage K
■2 is supplied to sound generation channels CH3, CH high tone voltage K ■3 is supplied to sound generation channels CH5, CH6, tone high voltage KV4 is supplied to sound generation channels CH7, CH8, respectively, and when movable contact e is located at fixed contact C, no sound is generated. High voltage KV
1 is the sounding channel CH, CH2, CH3, CH4,
Pitch voltage KV4 corresponds to sound generation channels CH, , CH6, CH
7, CH8 is supplied, and the movable contact e is further connected to the fixed contact d.
When the tone pitch voltage KV1 is located at , the tone pitch voltage KV1 is supplied to all sound generation channels CH1 to CH8.

That is, when fixed contact a is selected by movable contact e of switches 501a to 501g, one series of 8 tones is produced, when fixed contact b is selected, 2 series of 4 tones are produced, and when fixed contact C is selected, 2 tones are produced. When 4 series and fixed contact d are selected, the connection relationship is set in advance so that 1 note has 8 series.

Note that the tone pitch voltage KV1 is directly connected so as to be always supplied to the sound generation channel CH1.

Next, the second select switch 502, like the first select switch 501, each has four fixed contacts a = d.
An interlocking rotary type switch 502a provided with
~502g, and each of these switches 501a~502g
The movable contact e of 01g is for each sound generation channel CH2 to CH8.
are connected to each supply a key-on signal KO.

The second select switch 502 is configured to supply the inputted eight series of key-on signals KO, ~KO8 to each sound generation channel CH1 to CH8 while changing the series, and the connection relationship is that of the first select switch. This is the same as switch 501.

Therefore, in this second select switch 502 as well, when the movable contacts e of the switches 502a to 502g select fixed contact a, it becomes one series of 8 notes, when fixed contact b is selected, it becomes 2 series of 4 notes, and when fixed contact C is selected, it becomes 1 series of 8 notes. There are 4 series of 2 sounds, and when fixed contact d is selected, 8 series of 1 sound are created.

Note that the key-on signal KO is directly supplied to the sound generation channel CH1.

Next, the third select switch 503, like the first and second select switches 501 and 502, has interlocking gate-tally type switches 503a to 503g each having four fixed contacts a to d. , the musical tone control signals TM1 to TM8 to be supplied to the respective sound generation channels CH1 to CH8 are selected by selectively connecting the movable contact e to one of the fixed contacts a=d.

The connection relationship between the fixed contacts a% and d of each of the switches 503a to 503g is as follows.

That is, the movable contact e of each switch 503a to 503g
selects fixed contact a, musical tone control signal TM1
is commonly supplied to each sound generation channel CH1 to CH8, so that the eight series of sound generation channels are in the same musical tone state, and when fixed contact b is selected, the tone control signal TM1 is supplied to the sound generation channels CH1, CH3, CH, , CH7. Also, the tone control signal TM2 is applied to the sound generation channels CH2, CH4,
They are supplied to CH6 and CH8 respectively, resulting in two series of tones. Furthermore, when fixed contact C is selected, the tone control signal TM1 is supplied to the sound generation channels CH1, CH, and the tone control signal TM2 is supplied to the sound generation channels CH2, CH6. The control signal TM3 is supplied to the sound generation channels CH3 and CH7, and the timbre control signal TM4 is supplied to the sound generation channels CH4 and CH8, respectively, resulting in four series of tones.Furthermore, when the fixed contact d is selected, the timbre control signals TM1 to TM8 are supplied to the sound generation channels CH3 and CH7. The signals are supplied independently to each of the sound generation channels CH1 to CH8.

Each of the first to third select switches 501, 502 and 503 switches 501a to 501g, 502
a to 502g and 5038 to 503g are all interlocked and driven, for example, by operation of the switch control unit 504.

The pronunciation series control section 500 configured as described above can produce one series of eight tones, one series of eight tones, four tones, etc. by appropriately operating the switch control section 504.
By selecting one of 2 series of sounds, 4 series of 2 sounds, and 8 series of 1 sound, the first to third select switches 501
~503 switches 501a~501g, 502a~
502g, 503a to 503g operate in conjunction with each other, and a sound generation series is selected accordingly.

Therefore, in the normal state, one series of 8 tones is selected and each sound generation channel CH1 to CH8 receives the musical tone control signal TM.
1, the same musical tone state is set.

In this state, if you want to obtain the sound effect of an ensemble of piano and pipe organ, for example,
All that is required is to set the switch control section 504 to two series of four tones.

In this case, the pronunciation channel CH in charge of the first pronunciation series
1, CH3, CH5, and CH7 are to be controlled by the musical tone control signal TM1, and the tone generation channels CH2, CH4, CH6, and CH8, which are in charge of the second tone generation series, are to be controlled by the musical tone control signal TM2. , the musical tone control signal TM1 may be set to the musical tone of the piano, and the musical tone control signal TM2 may be set to the musical tone of the pipe organ.

In this way, musical tone control signals TM1 to TM8 of different musical tones (for example, piano, pipe organ, flute, etc.) are generated in advance.
By generating , you can freely set the number of pronunciation series within the maximum number of channels that can be sounded, and the same sound effect as when performing an ensemble can be created in a new sound channel. Easily obtained without addition.

Note that the connection mode of the first to third select switches 501 to 503 can be changed as appropriate from the illustrated embodiment.
In addition, each switch 5 of each select switch 501 to 503
01a~501g, 502a~502g, 503a~5
03g does not necessarily have to be all interlocked, and may be driven individually or in groups.

Musical tone forming section 600 Next, the musical tone forming section 600 includes a musical tone forming circuit 60 provided for each sound generation channel, as partially shown in FIG.
1a to 601h.

When looking at the first sound generation channel portion of the musical tone forming circuits 601a to 601h, the terminal voltage KV' of the capacitor 602 that charges the tone pitch voltage KV supplied from the first select switch 501 is input, It has a VC0603 that oscillates a sound source signal, a VCF5Q4 that controls this sound source signal to form a tone, and a VCA605 that controls the envelope of a musical tone signal. Envelope generator EG triggered by key-on signal KO supplied from 502
Controlled by 606-608.

And these envelope generators 606 to 608
generates a control waveform signal according to the musical tone control signal TM supplied from the third select switch 503.

The musical tone forming circuits 601a to 601h in charge of each sound generation channel CH1 to CH8 are configured in this way, and each musical tone forming circuit 601a to 601h has a first select switch 501, a second select switch 502, and a third select switch 503. Each independent pitch voltage K from
V, a key-on signal KO, and a musical tone control signal TM.

In the musical tone forming section 600 configured in this way, the tone pitch voltage K subjected to series control from the sound generation series switching section 500
When V is supplied, this pitch voltage KV is applied to the capacitor 60.
2, and the terminal voltage of this capacitor 602 is KV'
is supplied to the VCO 5Q3 to oscillate a sound source signal with a frequency corresponding to the terminal voltage KV/.

This sound source signal is supplied to the VCF 604, where the timbre is formed, and then supplied to the CF 605 where it is subjected to envelope control.

On the other hand, each envelope generator 606 607
At the same time as the tone pitch voltage KV is supplied to 608, a serially controlled key-on signal KO is supplied from the second select switch 502, and each of the envelope generators 606 to 608 starts operating in response to this key-on signal KO.

In addition, each of the envelope generators 606 to 608
is coupled to a musical tone control signal TM supplied via the third select switch 503, and each envelope generator 606 to 608 generates a control waveform signal for forming a musical tone state set by this musical tone control signal TM. VCO 6 0 3, VCF 6 0 respectively
4. Supply to VCA5Q5.

Therefore, the oscillation frequency of the VCO 603 is controlled in accordance with the control waveform signal supplied from the envelope generator 606, and the frequency characteristics of the VCF 604 are controlled in accordance with the control waveform signal, so that the pitch and A musical tone signal whose tone color changes is formed.

This musical tone signal is subjected to envelope control in the VCA 605 by a control waveform signal supplied from an envelope generator 608.

The musical tone signals generated from the respective musical tone forming circuits 601a to 601h are transmitted through the mixing resistors 900a to 9009.
The sound is generated from a speaker (not shown) connected to the output terminal 901 via 00h.

In this case, the tone forming circuits 601a to 601h are controlled to produce sound by the tone pitch voltage KV and key-on signal KO set by the above-mentioned tone generation series switching section 500 by selecting the number of tone generation series, and also by the third select switch 503.
The tone state of each tone generation series is controlled by a tone control signal supplied from the oscilloscope 100 for each tone generation series.

In this case, a gate circuit 609 is provided on the input side of each of the musical tone forming circuits 601a to 601h as necessary, and the conduction of this gate circuit 609 is controlled by the key-on signal KO, so that the input pitch voltage KV is This gate circuit 60
It is preferable to charge the capacitor 603 via the capacitor 9.

In this way, the gate circuit 609 closes when the key-on signal KO disappears as the key is released, thereby preventing a change in pitch of the musical tone during decay after the key is released.

Musical tone control signal memory 700 Next, the musical tone control signal memory 700 has a plurality of memories 700a to 700h corresponding to the maximum number of sounding channels, for example, as shown in FIG. 0a to 100h store independent musical tone control signals TM (voltage signals) for setting and controlling musical tone states such as the timbre and volume of musical tones, and the musical tone control signals TM are respectively stored from the memories 700a to 700h.
1 to TM8 are read out.

Each memory 70 of this musical tone control signal memory 700
Output signal 0a-700h, that is, musical tone control signal TM1
~TM8 is the third select switch 503 shown in FIG.
Here, the signal is supplied to musical tone forming circuits 601a to 601h corresponding to the set sound generation channel.

Therefore, by making the tone control signals TM1 to TM8 stored and set in the memories 700a to 700h different from each other, one of the 1, 2, and 4.8 series can be selected in response to the selection operation of the tone generation series switching section 500. The pronunciation based on the number of dead tone series can be obtained with different musical tone conditions for each pronunciation series, and as a result, it is possible to obtain a sound that is equivalent to an ensemble performance using different instruments of the selected number of pronunciation series. Musical sound effects can be easily obtained.

Note that in the embodiment described above, the pronunciation sequence switching unit 50
Although the case where the first to third select switches of 0 are configured by rotary type switches has been described, series switching may be performed using semi-moving body switching elements.

Further, although the tone control signal memory 700 has been described as having the same number of storage sections as the number of sound generation channels, it is not necessarily limited to this, and the number may be greater than or equal to the number of sound generation channels.

However, if the number of sound generation channels is greater than the number, one of them will be selected and used, and in the following cases, some parts will always be common to the sound generation channel portions of multiple series.

In the above embodiment, the musical tone forming section is constructed using a synthesizer type musical tone forming circuit, but the present invention is not limited to this, and it is possible to use a musical tone forming circuit using other types. Also good.

Furthermore, in the embodiment described above, in response to the switching setting of the number of sound series in the sound series switching unit 500, the input/output terminal 2 of the key depression state memory 204 of the channel processor 200 is
By controlling the channels 71a to 271h and the mode terminal 272, the number of channels assigned to sound generation in the channel processor 200 may be changed.

As explained above, the present invention provides an electronic musical instrument having a plurality of sound generation channels, in which key information and musical tone control signals assigned to the sound generation assignment channels of a key assigner are transmitted to one or more of the plurality of sound generation channels. Since it is configured to switch and control the supply, it is possible to generate independent musical tones on each channel in a specific number of sound generation channels (musical tone forming circuit), or to generate the same pitch in multiple sound generation channels. It is possible to selectively generate musical tones with different tones and volumes, and it has an excellent effect that various sound effects can be easily obtained with an extremely simple configuration.

[Brief explanation of the drawing]

FIG. 1 is an overall configuration diagram showing an embodiment of an electronic musical instrument according to the present invention, FIG. 2 is a diagram illustrating the representation diagram of logic elements used in this embodiment, and FIG. 3 is a diagram showing the timing signals shown in FIG. 1. A detailed circuit diagram showing an example of the generation section, FIG. 4 is a waveform diagram showing various timing pulses generated in the timing signal generation section shown in FIG. 3, and FIG. 5 is a diagram of the first key code memory shown in FIG. 1. 6 is a detailed circuit diagram showing an example of the key-on/off detection circuit shown in FIG. 1; FIG. 7 is a detailed circuit diagram showing an example of the truncate circuit shown in FIG. 1; 1 is a detailed circuit diagram showing an example of the key press information memory shown in FIG. 1, FIG. 9 is a detailed circuit diagram showing an example of the sampling control circuit shown in FIG. 1, and FIG. A detailed circuit diagram showing an example of a digital conversion circuit, Fig. 11 is a waveform diagram of each part to explain the operation of the sampling control circuit, sampling circuit, and analog-to-digital conversion circuit, and Fig. 12 shows the sound generation series switching shown in Fig. 1. FIG. 13 is a detailed circuit diagram showing an example of the tone forming section shown in FIG. 1. 100...Key coder, 200...Channel processor, 300...Key assigner, 400...Key code tone high voltage conversion section, 500...Tone generation series switching section, 501...
First select switch, 502... second select switch, 503... third select switch, 504... switch control section, 600... musical tone forming section, 700... musical tone control signal memory.

Claims (1)

[Scope of Claims] 1. A key assigner that assigns key information representing a key operated on a keyboard section to one of sound generation assignment channels corresponding to a plurality of sound generation channels that can be sounded simultaneously; a plurality of musical tone forming circuits that are provided and form musical tone signals corresponding to supplied key information; and determining which of the plurality of musical tone forming circuits the key information assigned to each sound generation assignment channel of the key assigner is supplied to. An electronic musical instrument comprising a pronunciation series switching section for selecting and setting. 2. A key assigner that assigns key information representing a key operated on the keyboard section to one of the sound generation assignment channels corresponding to the plurality of sound generation channels that can be sounded simultaneously, and a key provided and supplied corresponding to the plurality of channels. a plurality of musical tone forming circuits that form musical tone signals corresponding to information; a musical tone control signal memory that generates a plurality of musical tone control signals for setting and controlling a musical tone state to be formed for each of the musical tone forming circuits; and a sound generation sequence switching unit that selects and sets which of the plurality of musical tone forming circuits the key information assigned to the channel in each sound generation assignment of the key assigner and the musical tone control signal generated from the musical tone control signal memory are supplied to. An electronic musical instrument characterized by the ability to