JPS58124385A - Time axis correcting device - Google Patents

Abstract

PURPOSE:To attain time axis correction of a video signal very quickly and suitably, by driving an entire circuit system with an intra-station standard clock signal without using a clock signal locked to a tape H. CONSTITUTION:An input video signal such as a VTR reproducing signal is sampled with a sampling signal from a clock generator 15 synchronism-controlled with the intra-station standard clock signal at an A-D converter 1 to form a digital video signal, which is applied to a video delay device 2 and a synchronizing separator 9 in parallel. An input horizontal synchronizing signal for the tape H is separated at a separator 9 to generate 10 a burst flag, which is applied to a time axis error detector 6. The time axis error signal detected at the detector 6 is sectioned into a large error component in the sampling clock period unit and a small error component <= one sampling period, and the former is applied to a write start point controller 11 and the latter is applied to a time axis error delay device 7. The time axis error of the former is corrected by controlling the write start point in response to the amplitude of this error.

Description

[Detailed description of the invention]

The present invention corrects and standardizes time axis errors included in television video signals when reproduced from a video tape recorder VTR, etc., so that they can be mixed with other television video signals with an appropriate phase relationship. Regarding the time axis correction device, 1. . The time axis error contained in the VTR44+ raw signal, etc. can be quickly detected and corrected with high precision without any time delay. The basic operating principle of this type of time base correction device, that is, the so-called time base collector TBO, is that when a television video signal to which time base correction is to be applied is once written to a buffer memory and then read out, the correction side and readout side are 1
．． By independently controlling the timing of each side, writing and reading can be performed at appropriate timing [7
The first thing to do is... [7] In the conventional time axis correction device of this type, faithful to the above-mentioned operating principle, independent sampling clock threads are provided on the writing side and the bladder output side, and the sampling clock system on the writing side is connected to a VTR. horizontal synchronization signal separated from the playback video signal,
That is, the phase is locked to the so-called tape H, and
The sampling clock system on the read side is phase-locked to, for example, a horizontal synchronization signal supplied from an internal synchronization board, that is, the so-called reference H, and the reference H, from which the read clock is out of phase, is, for example, the output of a crystal oscillator. On the other hand, tape H to which the input clock is phase-locked has a phase that is constant and unchanging due to fluctuations in the tape speed of the VTR, so the tape has a phase-locked loop. The required phase lock was performed using a PLL. Therefore, in conventional time axis correction devices of this kind, feedback control of the PLL is slow in response, causing a delay in detecting time axis errors, and the error correction cannot be performed quickly and accurately. 1. There was a point. That is, for example, it is not possible to respond quickly enough to a large time axis error that causes distortion of the reproduced image, that is, so-called skew, when switching the video head in a VTR. (1) When configured with a single rotary head without using an auxiliary head such as a so-called sync head, there is a period during which the magnetic tape and the rotary head cannot come into contact, that is, a so-called head blanking period. For the video signal that is played immediately after,
Quickly. It is difficult to detect and accurately correct time axis errors, and regeneration of the sampling clock using a phase-locked loop PLL in conventional equipment has extremely disadvantageous drawbacks in terms of response speed and stability. Ta. It is an object of the present invention to eliminate the above-mentioned conventional drawbacks, and to correct the time axis of video No. 16 by appropriately adjusting the mutual relationship between the timings of clock signals used for writing and reading video signals to and from a buffer memory. In order to do this, instead of reproducing the write clock signal using a phase-locked loop PLL, which has a slow response and is unstable, as in the past, for example, the horizontal synchronization signal in the video signal reproduced from a VTR, that is, the so-called The tape H and the writing clock signal can be quickly synchronized in a so-called non-locking manner, so that there is no time delay until the tape H and the writing clock signal are synchronized at the same time as in the past. , input of video signal, or
In response to sudden occurrences of large time axis errors, tape H
Immediately from the time of entry, An object of the present invention is to provide a time 411b correction device 1 which can easily perform interaxial correction. 17 Thus, the present invention focuses on the fact that a predetermined phase relationship should exist between a television video signal of a predetermined system and a predetermined clock signal used as a reference within the station, and uses crystal oscillator output, etc. The input video signal to be subjected to time axis correction is sampled using the readout clock signal stably formed by the input video signal, and the time axis error of the input video signal is detected without delay based on the deviation between the sandal phase and a predetermined phase.
The sowing axis correction device is constructed by using the lock signal for 7 as the writing clock signal, which performs the necessary timing correction according to the time axis error. Since there is no phase lock relationship between the horizontal synchronizing signal in the input video signal and the writing 10x signal for tape H, etc., it is necessary to detect and correct time axis errors with sufficient precision. In other words, the time axis correction device 1 of the present invention corrects the time axis of an input image signal to produce an output car image having a reference time axis. Directly at the time axis correction device that forms the signal, each sample is sampled by a sampling clock signal having the time axis based on A11 in the reference signal waveform of the horizontal scanning period related to the Ail input image signal and the output image signal respectively. 1
Detecting a time axis error of the time axis of the input image signal with respect to the reference time axis based on the deviation between the input image signal and the output image 1 symbol of the mutual relationship of the plurality of sample values. a time axis error detecting means for detecting the sampled input image No. 1g, and a time interval between the sampled input image No. 1g and the sequence [7] of the time axis error, a time amount that is an integer multiple of the period of the sampling clock signal. a memory means for controlling according to a time base error component having a smaller time base error component having a smaller time amount than the period of the sampling clock signal of the previous time base error; clock phase modulation means for phase modulating a reference clock signal having the reference time axis in accordance with the reference time axis to form a phase modulated clock signal; The present invention is characterized in that the input image signal is sampled by the phase modulated clock signal I, and the input image signals successively output from the memory means are used as the previous output image signal. The present invention will now be described in detail by way of example embodiments with reference to the drawings. The basic operation of time axis error correction in the time axis correction device of the present invention, which has features based on the operating principle as described above, is to detect (-) the time axis error of the input video signal by horizontal Run L: A time axis error that is large enough to be discussed in comparison with the previous period H, a time axis error that is as large as several clock cycles that should be discussed in units of clock cycles equivalent to the pixel period, and small that is less than or equal to the clock cycle. The time axis error is divided into three stages and the time axis error of each stage is corrected as follows. By resetting the time axis correction system every time the tape H etc. is detected, the time axis error, which is large enough to be discussed compared to the horizontal scanning period H, is approximately corrected. (2) The present invention described in 1 to 1 above. Based on the operating principle of time axis error detection by
- Sample a known input signal waveform, such as a sine waveform of a color burst signal or a horizontal sync pulse waveform distorted by a predetermined low-frequency F-wave characteristic, using a tape H, etc. as a reference, and calculate the sample phase and standard method. Compare with the predetermined phase based on [2
Among the time axis errors detected in the process, the remaining time axis errors after the correction in step (1) described above are as large as several clock cycles, and are corrected by variable delay using a shift register. correction in units of clock cycles. (3) A small time axis error of less than 7 clock cycles that remains after the corrections in stages (1) and (2) mentioned above can be solved, for example, by using a digital circuit to correct the time axis.
The timing of the driving clock signal in the AD converter, DA converter, etc. is corrected by appropriately adjusting the phase modulation according to the residual time axis error. The eight stages of time axis correction described above can be performed in any order as long as the time axis error can be clearly divided into three stages. -F As mentioned above, the time axis correction of the video signal according to the present invention can be performed extremely quickly and accurately by driving the entire circuit system only with the internal standard clock signal.1.
Therefore, it is also possible to digitize the entire circuit system, and an example of the circuit configuration of such a time base correction device of the present invention is shown in FIG. In the illustrated configuration example, the analog-to-digital converter 1 synchronizes with an in-office standard clock signal, and uses a sampling clock signal of a pixel period from a clock generator 15 controlled by The input video signal is sampled, and a gain signal (, li', which has a 4-bit configuration, for example, is formed using an integer fraction of the sampling clock signal, for example, The synchronization separation circuit 9 separates and extracts the human horizontal synchronization signal from the tape H, etc., and supplies it to the burst flag generator IO, which performs the operation described in 7 above. A burst flag to be used as a timing reference for time error detection based on the timing is generated and supplied to the time axis error detector 6.The time axis error detector 6 operates as described in detail below based on the above-mentioned operating principle. Detection L~
The time axis error signal is divided into a large error component per sampling clock period and a small error component per sampling clock period, and the former is supplied to the start point controller 11, and the latter is supplied to the clock phase. Modulator 7
supply to. 17 or L-, to correct a large time axis error with a sampling clock period of I..., the digital video signal described above is supplied to the shift register (7 is taken out from the appropriate shift step and corrected by applying a variable delay. However, in the configuration example shown in the first diagram,
− of the digital video signal for time axis correction
By controlling the 1-include start point according to the size of the time axis error, a variable delay is applied to Tape I etc., and the tape is shifted to a position at an appropriate timing from the burst flag that matches the internal standard clock. Use H etc. for time axis correction. (12) [7] to write to memory address 300. In addition, the sampling clock IB from the clock generator 15
In order to compensate for the minute time delay of the digital video signal in the time axis error detector 6, the tape H delay device 14 driven by the synchronous separator 9 delays the raw tape H by the same amount as the time delay. This is to operate the write start point controller 1 at an appropriate timing. The configuration example shown in the first diagram is similar to other configuration examples described later, but the entire circuit system is digitized.
As shown in the figure, each component of the digital circuit operates under the control of the sampling clock signal from the clock generator 15 as well as the bit clock signal. , a detailed explanation will be omitted.
The digital video signal is appropriately delayed so as to be written to address 0, and the time delay of the gaintal video signal caused by the time error detection hanger 6 is compensated for, similarly to the tape H delay device 14. The memory controller 11 resets the write address of the memory 3 by the write start point control signal from the write start point controller 11. Memory addresses 1 to 300 are always set during the horizontal blanking period. The signal components at the same timing position within are written, and then sequentially at address 1, address 2, etc.
As the number of write addresses increases, the memory address and the horizontal timing position of the digital image signal component are in one-to-one correspondence. The internal standard horizontal drive pulse HD is appropriately delayed by the controller 18,
The time axis correction output video signal is phase-synchronized with the synchronization signal of the station synchronization board.
K and 1. By applying this to the memory 3, similarly to the write control, the read address of the memory 3 is reset by the continuous start control signal, and the read address of the memory 3 is sequentially read from address 0, 1, 2, 3, etc. ...and read out the gaintal image components. do. Furthermore, the clock phase modulator 8 converts the error component of the time axis error detection output signal that is less than or equal to the l-(+-1) clock period into a time axis error that is necessary to compensate for the minute time delay that occurs within the memory 8. The sampler clock signal sound received through the delay device 7 and has the same phase as the local standard clock signal from the clock generator 5 is phase modulated by its time axis error component, thereby approximately correcting the time axis error 17 A driving clock signal whose timing precisely matches the time axis error of less than one sunfling clock signal remaining in the digital image signal is supplied to the timing circuit 4 and the digital analog converter 5. Therefore, the timing circuit 1 uses the digital analog converter 5 to precisely match the time axis error of the digital video signal, and converts the digital video signal into a digital video signal when restoring it to the analog video signal No. 1. In order to accurately match the timing of the driving clock signal that has undergone phase modulation as described above, a minute time axis error is generated by appropriately delaying the clock signal for intimidation of the memory element and for continuous 12, for example. It is configured by component and phase modulated 7-1 driving clock signal as ! Okiwave device 5' removes unnecessary signals such as clock cycle components +3 components, and uses phase modulation that burns the standard clock signal within the station to generate a time @ 1 gap sleeve positive output analyzer.
1. Extracting the minute pixel points (after smoothing and removing 11 deviations of the pixel points occurring in the endogenous image of the video signal) as a corrected output video signal of the shaft stopper device a. In addition, - the timing circuit 4, which has a huge impact, for example, the vinegar of the shift register.

[It can be easily constructed by controlling and delaying the start point timing of the start point 7 using the start point control signal. In the configuration example shown in Figure 1, the above circuit operation (/(l
Therefore, the time axis error is corrected almost in advance 2, and the time axis correction is made so that it can be mixed and switched with other television images [Gizuki] at will according to the standard synchronous board system in the station. Output 11!1. ! - Image transmission can be obtained. 2 or 17, and in the configuration example of Figure 1, human power]
6 The time axis error of the video issue is divided into a large error component whose unit is Zanfling clock period and a small error component which is one sampling clock period or less. The latter precise correction is performed by adjusting the phase of the driving clock signal of the digital-to-analog converter from which the corrected output video signal is taken out, according to the minute time axis error of the in-office standard clock. [7] Therefore, when this corrected output image No. 16 is shown in its dimensions on an image display device driven by an in-house standard synchronous board, as described in 1 to 1 above, the clock signal for driving the converter is There is a positional shift of the reproduced pixels corresponding to a phase shift with respect to the internal standard clock signal, and the sampling structure of the reproduced image is not aligned in the vertical direction, resulting in image distortion such as a vertical straight line being reproduced and displayed in a jagged manner. Such irregularities in the sampling structure can be smoothed out using a low-pass filter as described in 7 above, but the corrected output image 1 of the time axis correction device of the present invention configured in a digital circuit.
If you take out the digital video in the same format as the digital video camera and supply it to other digital video equipment in that same format, the timing of the sampling clocks on both sides should be adjusted. This causes a misalignment, which is extremely inconvenient. However, there is a disadvantage due to the timing shift of the sampling clock, which requires a lot of effort. This can be easily done by performing steps 1-7 in the same manner as described above in the analog-to-gauge digital converter 1 on the manual side 1, prior to correction of large time axis error components. can prevent its occurrence,
Even without using the low-pass P-wave filter 5', it is possible to at least align the sampling structure of the reproduced image in the vertical direction, and the digital video signal of the time axis correction output can be directly sent to the trench or other digitized video equipment. can be supplied. As mentioned above, an example of the circuit configuration of the time axis correction device of the present invention in the case where small [Terama axis error correction of one sampling clock cycle or less] is performed in the analog-to-digital converter on all input sides, and feedforward control is further performed. is shown in Figure 2. Therefore, most of the configuration example shown in the second diagram is the same as the configuration example shown in the first diagram.
Therefore, an explanation of the circuit operation will be omitted, and only the differences (7) will be explained.
A major difference from the illustrated configuration example is that two analog-to-gauge converters 1 and 1' are placed side by side on the input side. One of the analog-to-digital converters 1 is operated by the sampling clock 218 and the pit clock signal from the clock generator 15 which is phase-synchronized with the internal standard clock signal, and the converted output digital video signal is synchronously separated. The steps after separating and extracting the human-powered horizontal synchronization signal of the tape H chopsticks used for time axis error detection according to the operating principle of the present invention are carried out in the same manner as in the configuration example shown in FIG. The time axis error obtained in IE 1 is divided into a large error component in units of sampling clock periods and a small error component in units of one sampling clock period or less. However, the point shown in Figure 1 is that the correction of the latter time axis error component smaller than one sampling clock period is performed by the analog-gauge digital converter 1' on the input side. There are significant differences from the configuration example.In other words, in this analog-to-digital converter 1', the input analog image signal is digitized while correcting the time axis error smaller than the sampling clock period. 7, the digital video signal is supplied to the timing circuit 4 prior to the video delay device 2 similar to that in the configuration shown in FIG. In order to match the timing of the clock signal, a circuit configuration similar to that in the configuration example shown in FIG. The digital itT++ image signal at the appropriate pixel position, which is converted into a sacred tree by the phase modulated sampling clock from the phase modulator 8, is converted into an analog-digital signal. It is received from the converter 1', written to the memory element at the timing of the phase modulated clock signal, and read out at the timing of the in-office standard clock signal.Therefore, the gage digital image signal with such timing correction is processed. The time-base corrected output analog image signal, which has been subjected to large time-base error correction similar to that in the configuration example shown in FIG. The vertical irregularity of the sampling structure, which was a problem in the configuration example shown in FIG. In the configuration example shown in Figure 2, two analog-to-gauge digital converters 1 and 1' are used on the input side as described in 17 above, but of these, the analog-to-gauge digital converter is exclusively used. Used to detect time axis errors, analog
The digital converter 1' is used exclusively for correcting minute temporal eye differences. However, since the time axis error is detected only during the horizontal period, as will be explained later,
By paying attention to this point and switching between the horizontal blanking period and the video period, it is possible to reduce the number of analog-to-digital converters on the input side to only one in the configuration example shown in the second figure. That is, one analog-to-digital converter is provided on the input side, and the clock generator 1 is used during the horizontal blanking period during which time axis error detection is performed as described later.
The internal standard clock No. 214 '-' is supplied from the clock phase modulator 8, and the phase modulation sampling clock Gozuki from the clock phase modulator 8 is supplied during the video period in which -' and small time axis error correction is performed. It can be used by switching. At the time of the present invention, the circuit configuration was changed as described above. An example of the configuration of the interaxial correction device is shown in FIG. In the configuration example shown in Figure 3, an analog-to-digital converter 1 is provided on the input side.
11, which is provided with a
7, time axis error switch 18, and clock switch controller 16 added 1. In the clock switch 17, a sampling clock signal 1 to 1 is supplied to the analog-gauge digital converter l and the timing circuit 4, and a phase modulation sampling clock signal from the clock phase modulator 8 is supplied between the video JtJ1. On the other hand, in the time axis error switch 1.8, the clock is switched as if it were a signal.
. The time axis error signal component to be supplied as the basis is used as a basis, and the time axis error is switched by using the minute time axis error component as described above (7) during the video period, and furthermore, the clock switching controller] In 6, manual image 1 such as tape H
23 Forming a ranking signal [7, - A switching control signal for performing the above-mentioned switching and applying it to each switching device 17 and 18 at 1-7. At the same time, each component commonly used in the configuration example of the time axis correction device 4 of the present invention shown in FIGS. 1 to 3 will be explained in detail. To explain the time axis error detector 6, the operating principle of time axis error detection according to the present invention is as described above in section 7. Based on the predetermined phase relationship that exists between the local standard clock signal and the internal standard clock signal, the input video signal is converted to the local standard clock signal. The objective is to be able to detect the time axis error of the image without any delay, and it is based on the same operating principle as No. 4 of the color signal when receiving the standard/system television image volume. Yes, the input horizontal synchronization signal of DenoH is also 1. Form 1 by applying a slow daughter to the horizontal 1i1 period signal. At step 17, a known predetermined signal waveform in 24+ of the input video signal waveforms is sampled based on the burst flag signal obtained (step 7, two signal components that should maintain a mutually orthogonal phase relationship are calculated,
Calculate the arc tangent by taking the ratio of the two orthogonal components, and from the arc tangent, 1. By calculating the sun sill phase angle and converting that sun shilling phase angle into a time scale, it is possible to obtain a signal that maintains approximately one frame even in the subsequent image period, based on the input horizontal synchronizing signal of tape H, etc. □ Quickly detect time axis errors within the horizontal blanking period without delay.
It was made so that it could be released. Based on this operating principle, a standard clock signal of 1. FIG. 4 shows an example of an aspect of time axis error detection according to the present invention when a color burst signal is used as a known signal waveform that should have a predetermined phase relationship. The illustrated color burst signal waveform is an example when the frequency of the standard clock signal is equal to four times the color burst frequency. In the illustrated example, one cycle of the sine waveform forming the color burst signal is divided into four points. sampling (7, each sample level 'i''1.n + 2.n + a,
n+x4. Let it be n. Note that the subscript n indicates that the nth sine wave in the color burst signal is sampled once again. (7), the 4-line width of the color burst signal is A and 12, and its DC level is B and 12
, furthermore, the sample level X1. , H at the sampling point is θ, the above-mentioned sample levels at each sampling point are expressed as follows. Xi n =B+ASinθ
(1)X2. n-B+As1n(θ+90°)-B
+Acosθ (2)X8. n-B+A sin (
θ+180°)-B-Asin θ (8)X4 n
= B+As1n(θ+270°)=B-A008
θ (4) Here, the difference between the two sample levels that should be exactly in antiphase with each other, that is, X(1) and X8. n
(3) and 1, the difference between n, and X2. n(2) and X4. The difference between n(4) and n(4) is calculated as follows. X1n-x8n=2ASinθ (5)X2n
−x, n=2Acosθ (6) The sample level difference (5), (6) is calculated for the entire color burst issue by truncating both the front and rear ends to remove the effect of the passing phenomenon. By integrating the color burst effect only in the central portion, the following two signal components having mutually orthogonal phases are obtained. Knee −Δ”(x −x ) (7) Sln
nl, n8. n For such orthogonal two-component work, if we calculate the arctangent by taking the ratio of □n(7) and 1°O3(''), we get the colorverse +
The sampling phase angle, ie, the time axis error, for the -S=- waveform can be calculated. It should be noted that when the sample phase θ at the earliest sampling point mentioned above is θ−〇, the time axis error is zero, and the range of values in which the sample phase θ can change around this time axis error state is Assuming that is -18 (10 to +180 degrees), the sampling phase angle of the color burst chemical expressed by this earliest sample phase θ is as follows.7 Convert this sampling phase angle to time 'l'. for,
Since the color burst frequency is 1/ of the standard clock frequency, the phase angle of 90° can be regarded as the clock period and can be replaced by +2 according to equation (9).
It is possible to detect a time axis error in the range of time corresponding to the clock period - M7. As mentioned above, an example of the configuration of the time axis error total detector according to the present invention is configured to detect all the time axis errors of the input image by using only the standard clock number 1 in L2 for the colorverse L-Tsukuduki. It is shown in FIG. In the illustrated example of the configuration, the shift register 19 is
-1 Manually powered digital image signals driven by standard clock signals within all stations, supplied in series to the shift register 19, taken out in parallel at the phase interval of the clock cycle, and sent to each D flip-flop 20-1 to 20-4, respectively. 4-phase digital images obtained for 41 sampling points every 8 cycles of input color burst toy No. 1. n+
8. n+X4. n over multiple cycle periods I
~Take it out. -1, 22-2 and D flip-flop 28-1°2
It is supplied to a pair of integrators configured by the combination of 8-2, and the 4★ component is applied according to equations (7) and (8) described in 11. [7, The integrator is connected to a pair of latch circuits. 24-1.241
-2. The pair of latch circuits 24-1. In 241-2, a burst flag pulse appropriately formed to have a pulse width corresponding to at least a plurality of cycle periods in the central part of color burst No. 1H in a human image signal is externally transmitted to the 111 edge detector 26 and the trailing edge. Supplied to the detector 27 (at the trailing edge of the burst flag pulse detected at -7, the above-mentioned result is latched by -H, and the arc tangent unit 25 lead to,
According to Equation (9) described by Air, the time axis error signal is all taken as the arctangent of the orthogonal two-component signal. Note that the front pulse of the burst flag pulse detected by the above-mentioned leading edge detector 26 is
-1.28-2 for each horizontal scanning period, and also clears the flops 20-1 to 20-4. and ■ generate the above-mentioned single lock signal for driving 28-1.28-2i. -Also, the arctangent unit 25 may, for example, store in advance arctangent values corresponding to all combinations of the above-mentioned orthogonal two-component signals in the range that can occur in the field A.
It can be easily configured using JROM. 1, [7] As mentioned above, the deviation of the relative phase from the appropriate value between the known signal waveform in the human image signal and the local standard clock signal, that is, the time axis error based on the phase error. For detection, if a color burst signal is included in the input image No. 15, as described above, it is preferable to perform time axis error detection according to the present invention on the color burst signal (in step 7). However, if the input image signal does not include the colorverse, the time axis based on the phase error is similar to that described above for the horizontal synchronization pulse waveform of tape H, etc. Error detection can also be performed, and examples of phase error detection in such a case are shown in Figures 5 (a) to (0). This figure shows only the rising edge of the horizontal synchronizing pulse, which is guided to a low-pass P-wave generator with a predetermined tilt and allowed to decay appropriately. When sampling is 1- with a sampling clock phase-synchronized with
Time l1 of the input image signal relative to the internal standard clock signal
111 When the error is zero, ~3 as shown in (a) of the same figure.
The sampling point is located almost on the slope of the rising signal waveform (assuming that the same horizontal pulse is generated). In other words, the sample levels at the three sampling points are sequentially set as X 4 , X 2 , Xs (Once again, time axis converter case 3) In this case, the second sampling point indicating level [7] Then, the ratio of the difference in sample level between the three sampling points and the adjacent point R is as follows: x2-x. If converted into axes, the time axis error of the human image 1V can be obtained in the same way as in the above example, and as shown in FIG. 6(a); the level difference between the three sampling points is equal L7<, When R=1, the time axis error is zero. Also, as shown in the figure (+), x8−
x2>x2-x, and when R>1, the phase is leading; as shown in the same figure (C), x8-x2<x2-Xl, and when R<1, the phase is lagging; All axis errors can be calculated. As shown in 1E above, the structure of the time axis error detector 32 according to the present invention is 17, which targets the horizontal synchronizing pulse in the input image signal. Some examples are shown in Figure 7. In the illustrated (14-channel system), the human-powered digital image signal whose time axis error is to be detected is detected using a low frequency t having a predetermined passband characteristic. The horizontal synchronizing pulse waveform supplied to the shift filter 29 is made to have a predetermined slope as described above, and then the shift register 19
are supplied in series (~, as described above in Fig. 6).
3 supply 17, sync separator 5) and tape H delay device 1
4, the subtracter 2
]-1゜2 ]--2 and time axis converter 3 f) l
From /c, the sample level difference ratio R is calculated according to the above-mentioned equation (10) 12, and the time axis error is determined by converting it into a time tone. Note that, like the arctangent converter 25 in the above-described configuration example, this time axis converter can be easily configured using a read-only memory 17 for storing all required data. The tape H delay device 14 in the circuit system that separates and extracts horizontal synchronizing pulses such as tape H from the shunted input image signal processes the time delay caused by the low-pass filter 29 of the input image signal, which is the 71st aspect of time axis error detection. There is no compensation. Next, the mode of time axis correction applied to the input image signal based on the time axis error detected as described above will be described in detail. First, regarding the correction of large time axis errors that should be discussed in units of sampling clock cycles, the writing start point to the memory device to correct the time axis of the input image signal is adjusted in units of clock cycles by adjusting the timing of writing and cooking. Control according to the size of the time axis error component,
This can be achieved by applying an f-variant delay. FIG. 8 shows an example of a circuit configuration that performs time axis correction in this manner. In the illustrated circuit #4, an input horizontal synchronizing pulse train such as tape H is supplied in series to a shift register 19, and the intermediate stage of the shift register 19 with an interval of 2 l sampling clocks is connected in parallel to a data selector 31. Shift, among the delay pulses obtained from those intermediate stages, those with appropriate timing centered around the delay pulses with intermediate slow abrasion, and 1 to 1, the delay pulses obtained from the intermediate stages are divided into sampling clock cycles within an appropriate delay amount range. A data selector 31 selectively extracts delayed pulses after timing correction. Next, correction of a time axis error smaller than one sampling clock cycle is performed using the analog-to-gauge converter on the input side of the time axis correction device of the present invention, as described above with reference to FIGS. 1 to 3. [7] It is preferable to use a digital-to-analog converter on the output side. This is achieved by applying phase modulation. Configuration examples of such a clock phase modulator 8 are shown in FIGS. 9 to 11.
As shown in the figure. In addition, all of the illustrated examples are ≠. 1. Binarize minute time axis error components with 4 bits for a time smaller than the clock cycle. The circuit configuration in the case of
Of course, it is something that can be obtained. In the example shown in FIG. 9, the clock phase modulator 8 is configured in parallel, and the sampling clock period i1
The data selector 31 is constructed by connecting 15 clock delay elements 33-1 to 33-15 in series, each having a delay amount equal to the time length divided into six, and providing an intermediate tap at the input/output terminal of each clock delay element. (7) A delay IA equal to the internal standard clock signal supplied to the clock delay element series circuit 38 via the buffer amplifier P32.
100 delay clocks having a standard clock period of 7 and which are sequentially applied are supplied to the data selector 31 in parallel. The data selector 81 is separately applied with the above-mentioned minute time axis error component converted into a binary value with 4 bits, and selects a delayed clock signal having a delay amount corresponding to the error amount (1 to 1). Next, the example shown in Fig. 10 is a clock phase modulated 6 clock signal which is configured in a SkiM array type, and has a binary signal representing a minute time axis error component. The data selector 31-1 selects 4 clockers 36 corresponding to successive bits in a natural binary code having an equal number of bits (7) having sequentially weighted delay amounts, for example, in descending order of the delay amount.
.about.81-4 are connected in cascade afterward, and the total amount of delay due to each delay element is equal to the sampling clock period, which is 7. Also, each deru. The standard-cycle sampling clock signal supplied to the series circuit having such a configuration via the buffer amplifier 32 is converted to each data signal corresponding to each successive bit by the selection operation of each data selector 31 according to the amount of time of the minute time axis error component. via a clock delay element, or
The signals are short-circuited and sequentially sent to subsequent stages, where they are taken out as a phase-variable clock signal. Next, in the example shown in FIG. 11, the clock phase modulator 8 is configured in a series-parallel type, and three sampled clock delay elements 85-1 to 35-3 are connected in series and each Data selector 31- with input/output terminals as intermediate taps
Three clock delay elements 33 connected in parallel to 1 and configured similarly to the parallel type shown in FIG.
-1 to 33-3 and the data selector 31-2 configured in the same manner are connected in series to form a series-parallel circuit, and the aforementioned binary encoding minute time is applied in parallel to each data selector 31. Controlled by the axis error component, a phase modulated clock signal formed by applying a delay similar to that of the parallel type shown in FIG. 9 and the serial type shown in FIG. 1O to the standard sampling clock signal supplied via the buffer amplifier 32 is extracted. The digital circuit in the configuration example shown in FIGS. 1 to 3 is driven by the phase modulated clock signal formed as described above to correct the aforementioned minute time axis error component included in the input image signal. - The analog converter 5 or the analog-to-digital converters 1, 1' is provided with a timing circuit 4 before or after the analog converter 5 or the analog-to-digital converters 1, 1' to correct the timing of the digital image signal of the respective conversion input or conversion output. The timing of the output digital image signal and the internal standard clock signal is adjusted. FIG. 12 shows an example of the configuration of a timing circuit that performs this function. In the illustrated configuration, a data switch 37 inserts the period 36 of the internal standard clock signal between the two D flip-flops 20-1 and 20-2, or switches the connection to short-circuit them. The uppermost pit signal of the binary encoded minute time axis error component described above is also applied to each D flip-flop 20-1 and 20a9.
- When correcting minute time axis errors contained in the output side tintal-to-analog converter 5, the clock input
The clock signal 2 is a phase-modulated clock signal, and the above-mentioned correction of the minute time axis error is inputted as in the configuration example 7 shown in FIGS. 2 and 3. If this is done in the analog-to-digital converters 1, 1' on the side, each clock signal 1 and 2 will be the opposite of what has been described above. 17 and each D free lag flop 20. -1.20-2, the digital image signal is supplied to input cat 1 and latched by clock signals 1 and 2, and if the timing difference between the two is severe, one clock signal is applied between the two. By applying a period delay, the timing circuit 12 having the illustrated configuration can be configured to have a period delay. The timing of the digital image signals of the human power system and the output yarn, which are respectively operated using different clock signals, is synchronized. Therefore, in the explanation in Section 1, all corrections for the time axis errors included in the image signal are performed in the form of forward-forward control.
The time axis error correction can be similarly performed in the form of feedback control without being limited to this example. FIG. 18 shows an example of the configuration of the time axis correction device of the present invention in the case where such feedback control is carried out. In the configuration example shown in the figure, the synchronization separator 9, the time axis error correction/horizontal synchronization position modulator 39, and the clock phase modulator 8 are connected via the integrator 38 in an overall configuration that is roughly similar to the configuration example shown in the third figure. It constitutes a feedback loop, but this 1.
The feedback loop does not act as a phase-locked loop PLL on the drive clock signal as in the conventional device, but as is clear from the figure, all the clock signals that drive this feedback loop are looped from the clock generator 15. It is supplied independently of the connection and is not subject to any locking action. That is, although the configuration example shown in FIG. 13 is in the form of feedback control, the basic configuration and l- are similar to the configuration examples shown in FIG. 8 or 2, and a clock having a certain phase is used. Assuming that a signal exists and that the input image signal is sampled using the clock signal, the time axis error of the sardine based on the operating principle of the present invention described above is detected. In the configuration example L7 shown in FIGS. 3 to 2, the clock signal having a certain phase described above is the clock signal that drives the entire device w, that is, the internal standard clock signal, and the time axis correction is performed using this internal standard clock. The entire phase of the signal is used as a reference, and time axis correction is performed by applying phase modulation corresponding to the time axis error to the internal standard clock signal.If you think in the same way, the 13th In the illustrated configuration example, the clock signal having a certain phase is a clock signal obtained by sampling the image signal of the horizontal scanning period that has already undergone time axis correction immediately before the hydrophilic half-scanning period that is the target of time axis correction. , the time axis difference is detected and corrected using the time axis corrected clock signal. In addition to detecting all, the time l1q11
The method is to phase modulate the clock signal according to the error. Therefore, it is useful for time axis correction between the immediately preceding water, Y, and fw3 (currently horizontal scanning on the time axis correction side (foundation) old publication), and the time axis error detected as described above between IJJ can also be added. Specifically, all that is required is subtraction, and I2< is the sum of the time axis errors due to subtraction (1)
This is done by an integrator 38. In other words, if 'FL' is :lff*-'F scanning period image 1, unless it contains a time axis error, the time axis correction system ja11 used in the preceding horizontal scanning period can be changed based on the information ff3. If the image signal during the current horizontal scan (v) contains a time axis error, the time axis can be adjusted according to the time axis error. However, [2] As shown in FIGS. 1 to 3 and 13,
However, in the configuration examples of the time axis correction device of the present invention, the color burst signal is also generated at the beginning of the sequential horizontal scanning period and the horizontal erasing period of the human-powered image No. 16 (see the horizontal opening 10). After completing the time axis and 4.3 error detection and correction in several months and 17, continue with 111II.
It is assumed that there is almost no change in the time axis error 1 even during the image period [7] The state of the time-11 correction performed at the beginning of the horizontal scanning period is assumed to be the same as that 1 during the horizontal scanning period.
For example, due to a constant deviation in the tape speed of a VTR, even during the image period, the tape is maintained continuously.
"Change t in the time axis error door that occurs linearly in ~", ignored 17
, the so-called 1-level error correction that corrects continuous and white line changes in the time axis error amount is omitted, but the speed at which changes in error during the image period are corrected is corrected. It goes without saying that the above-described time axis correction according to the present invention can also be used in combination (7 to 8). An example of the configuration of the main parts of the axis correction device is shown in the 14th section.
As shown in the figure. In the configuration of the main part illustrated, for example, the time axis error signal detected by the time axis error detector 6 is supplied to the D flip-flop 2o, and the horizontal cycle IL in the image signal is
Ji 17< is also activated by a signal related thereto, for example, depending on the application of the readout [~start point control signal 4111]. Therefore, since the time axes at the beginning of each of the adjacent horizontal scanning periods that continuously change in a plane are present between the two output terminals of the D flip-flop 200, the time axis error between them is taken into account. Linear interpolation between the two is performed by supplying the signal to the interpolation circuit 41 and changing the depth linearly.
1-1 by applying a clock signal to the clock phase modulator 8 to perform phase modulation according to the internal standard clock signal and its interpolation error l.
Such a phase modulated clock signal is supplied to the timing circuit 4 and the digital-to-analog converter 5 in the same manner as in the configuration example shown in the first figure. Note that the timing circuit 4. If the digital images are to be supplied sequentially to the digital-to-analog converter, they are supplied via an IH delay line 40 to compensate for the time delay 'i'1 caused by the interpolation circuit 4.1. 1. The one-degree error correction circuit configured as shown in the figure is inserted in front of the digital-to-analog converter on the output side in any configuration of the present invention apparatus, especially in the configuration example shown in the first figure. , the clock phase modulator 8 and the timing circuit 4 are connected in cascade to both the time east 11 error correction and the speed error compensation described above, but each clock phase modulator 8 and the timing circuit 4 are connected in cascade. It is also possible to share the circuit 8 and the timing circuit 4 for both. As is clear from the above gt2 light, according to the present invention,
Playback from VTR 1. Conventionally, errors in the time axis of an input image signal such as a digital image signal were corrected by differentiating the timing of the clock signal used for 1 loading and reading 17 for the memory element. In the same case, using only the internal standard clock No. G [BJ axis error correction is performed, so the phase synchronization between the writing clock month and the horizontal synchronization signal of the input image signal of tape H etc. is not possible as before. If the input horizontal synchronizing signal of tape H etc. is detected without any delay, it will be processed immediately without any delay. By detecting axis errors and correcting them, it is possible to quickly and accurately obtain an image signal with an appropriate time axis that is phase-synchronized with the local standard clock. In other words, in which month is the writing clock and which month is the reading clock for the memory element for time axis correction?
- Since the clock signals from the source are commonly used, memory control is extremely easy, and signal processing within the device is performed by sampling the image signal using these clock signals. In particular, a high degree of stability and fidelity can be easily obtained.
Detection of time axis errors based on the operating principle of the present invention used in the structure 1 example shown in Figure 1 is repeated 1. It is possible to obtain the advantage that the detected time axis errors can be accumulated by 1 to 1 to reliably eliminate the errors. As mentioned above, the time axis correction device of the present invention
The VTR has a painfully fast response speed to the occurrence of 4I errors and is used for recording and reproducing high-quality color preview signals.
-C is extremely suitable as a time base correction device a to be used together with the time axis correction device a, and can be said to be ideal. Well, in the luminance signal/chrominance signal separation recording and reproducing method, even if a time axis error remains at 4.7 in the writing signal, the remaining time error in the luminance signal falls in the horizontal direction of the reproduced image. It only appears as a slight positional misalignment, and the remaining time of the reproduction color 1 lucky number 11
111 error is totally visible, whereas
Composite color television 1 in which a luminance signal and color 1C are multiplexed 1~1@Blue is recorded in the 1G format of 1000 ox-ma. -The time axis error remaining in the composite signal appears as a phase rotation of the conveyed color signal, that is, a shift in the color phase, resulting in a total deterioration of the reproduced color image quality. [7.Therefore, in the Brilliant #Chemical/Colored Boar Separate Recording Ceremony, Xu Yunren Mimi--The application of the time axis sleeve clasp according to the present invention is the combination of the above-mentioned [7] speed error sleeve IE. Although it is unpleasant, the luminance/color combined signal power method was originally intended to be used in combination with VTRs for recording and reproducing high-quality color television signals in order to avoid deterioration of reproduced color image quality due to the residual time axis error mentioned above. Although the time axis correction device of the present invention performs wideband, stable time axis correction to make the color blue, it is not possible to record a color television signal of the current standard ``J:J type''. However, as long as the target is a color image signal of the single brightness/color extraction combined force type, it is necessary to use speed IW error correction in order to reduce the residual time axis error. Note that the time axis correction of the present invention Equipment ρi4. 1. VTR
Appropriate changes were made not only to the reproduced image signal from the 1. It can be applied in the same way and the same effect can be achieved.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a configuration example of the time axis correction device of the present invention, FIG. 2 is a block diagram showing another configuration example, and FIG. 3 is a block diagram showing still another configuration example. 4 is a signal waveform diagram showing an aspect of time axis error detection according to the present invention, FIG. 5 is a block diagram showing an example of the configuration of a time axis error detector according to the present invention, and FIG. 6(a), ■)
, (C) is a signal waveform diagram illustrating another embodiment of the time axis difference detection according to the present invention in full sequence, FIG. 7 is a block diagram illustrating another configuration example of the time axis error detector according to the present invention, and FIG. The figure is a block diagram showing a configuration example of a memory write start point limiter according to the present invention, FIG. 9 is a plotter diagram showing a configuration example of a clock phase modulator according to the present invention, and FIG. A block diagram showing a configuration example, FIG. 11 is a block diagram showing another configuration example, FIG.
2 is a block diagram showing a configuration example of a timing circuit according to the present invention, FIG. 13 is a block diagram showing still another configuration example of a time axis correction device according to the present invention, and FIG. It is a block diagram showing an example of the configuration of the auxiliary IE device. 1. l'...Analog-gauge digital converter, 2...
Video delay device, 3. Memory element, 4. Timing circuit, 5.
Tishitaru analog converter, 6... Time axis error detector, 7-- Time axis error, 1! ! 8 Clock phase modulator, 9... Synchronization separator, 10 Burst flag generator, 11 - Write start point controller, 12 Memory controller, 13 Read j2 start point controller, 14... Tape H Delay device, 15 ・Clock generator, 1G tarot switch @ device, ]] 7 Clock switch, ] 8 Time axis error switch, ]] 9 Horns. Tre register, 20.20-1 to 20-41, 23,
. 23-1.23-2...D flip-flop, 21°21-1.21-2-subtractor, 22.22-1. 22-2... Adder, 24.24-1 to 24-3... Latch circuit, 25... Arctangent, 26. Leading edge detector, pass filter, 30 Time axis converter, 31.31- 1-3
1-4...Data selector, 82...Buffer 87...
-Data switcher, 38.Integrator, 39..Tape H position modulator, 40..IH delay device, 41..Interpolation circuit. (51ゝUnexamined Japanese Patent Publication No. 58-124385 (ZO) Procedural Amendment 1989 ``February 26 [1]'', Case Description Showa 1957 Ner Wf Petition No. 6827
>9-2, Name of the invention Time axis correction device M 3, Relationship with the heavy stone incident (4135) H Broadcasting Association 7, Contents of the amendment (Betsume Kou)) IIJ '1I)) - (correction) Akira
Details v9 1 Title of the invention Time axis correction device 2, % permission request! jλcircle L time! 1 Illll error including input TV staff -
Utilizing the reference signal during the process, the entire time difference is detected [7,
In the input television error correction device, which is applied to the time axis wholesale control means, it consists of the previous day's time axis system and 111 means stages, ] According to the reference horizontal scanning periodic signal of the reference M 1M'-"r, . IN self-reference color code time 1 [41] Due to the error of 1 clock unit, the previous ml shift register / fljll starvation 12, and the constant period and time 1
Clock color - Time within one clock cycle to the bow ■ Variable R'4 clock 18 with phase modulation according to axis error
Controlling the sample means with a spoon (7. A time axis correction device characterized by correcting the time ill of a human-powered television signal; (d
A time axis correction device characterized in that the reference signal is a water signal in an input Kaprevision Iha signal. ＆Special bar: In the time axis correction device described in item 17 of 11f, the reference number 1 is the input television 1.
In the time axis correction device described in item 1, the time axis correction device is characterized in that it is a burst number in the burst number 8'' [R8 4% ff 0 range]. [7] A time axis correction device characterized in that the tenth stage of the Air sample is a D/A converter for PCM. FL The time axis correction device h according to claim 1. ′
, the time axis control is processed using the POM television signal, and the sampling means i1: A for POM.
1), in which the /D converter and J are compatible, is an interaxial correction device. 3. Detailed Description of the Invention The present invention corrects and standardizes the time axis error that occurs when playing from a vinyl tape recorder VTR. For example, when mixing with other television video signals in a proper relationship (7), it is time to mix the signal with the correct position (7).
This German time axis correction device [4=, that is, 7.] L
ψ Time Base Collector TBO's Basic 41υ Promotion 1"! (7) Interphase axis correction' (i- All addresses of the television video signal to be applied can be controlled.
< is written to the analog type buffer memory once and then
Please check the timing of the collection side and the start-up side before 11th.
By carrying out fall (711) independently for each L, it is possible to carry out the input and readout of the V iron at a consistent timing.However, in the conventional effi of this type of time 4 time 11 sleeve correction device effi, the above-mentioned operation is performed. Faithful to the principle, each side has an independent sampling clock system, and the sampling clock system on the writing side is phase-locked to the horizontal synchronization signal extracted separately from the VTR playback video signal, that is, so-called tape H. In addition, the sampling clock system on the bladder output side is phase-locked to a horizontal synchronization signal supplied from, for example, an in-station synchronization board, that is, the so-called reference H. The base 4!H that phase-locks the readout 17 clock is For example, tape H whose phase is fixed based on the output of a crystal oscillator is fixed, whereas tape H whose phase locks the write clock has its own phase.
Because the phase of the tape varies due to variations in the speed of the rotating head, etc., a phase-locked loop PLL is used to lock the phase. Therefore, this conventional one
In the time axis correction device, since the PLL performs feedback control, the response is slow, and the VTR playback
Obtain g issue 1. Phase lock is applied to the clock after
However, there is a delay in the process, and the time axis error cannot be corrected quickly and accurately. That is, for example, V
To deal with the distortion of the reproduced image that generally tends to occur in response to t1 when switching the video head in TR, that is, when there is a large change in time axis error such as the so-called skew phenomenon, [7] 1. When a business-use helical VTR 1 is constructed with a rotary head at a rate of 100 mm without using an auxiliary head such as a so-called sync head, the magnetic tape and the rotary head come into contact [7]
During this period, tape H is partially missing (7), so the anti-phase lock of the write clock is completed. It is difficult to quickly detect and accurately correct time axis errors, and regeneration of the sampling clock using a phase-locked loop PLL in conventional devices is extremely disadvantageous in terms of response speed and reliability. An object of the present invention is to eliminate the above-mentioned drawbacks of the conventional technology and to appropriately adjust the mutual relationship between the timings of clock signals used for storing and reading video signals from a backup memory. When correcting the time axis of the video signal by Since all decoding is used for land use, there is no delay in synchronizing the tape H and the clock signal for recording, as in the conventional case, and there is no need to worry about the incoming video signal or large time axis errors. It is an object of the present invention to provide a time axis correction device # that is capable of immediately responding to the sudden occurrence of the problem and immediately correcting the time axis from the time when the tape H is received. Focusing on the fact that there should be a predetermined phase relationship between the television image declination angle and the predetermined synchronization signal and clock signal that serve as the reference within the station, we Loading and reading from buffer memory using synchronization signal]7
The input video signal to be subjected to time axis correction is sampled by the readout clock No. 4M stably generated by the control and the output of a crystal, etc., and the deviation between its yumble phase and a predetermined phase is calculated. This volatile time axis correction device is constructed by detecting the time axis error of the input video signal without delay and performing timing correction on the video signal according to the time axis difference. The time axis correction device of the present invention utilizes a reference signal in an input television signal including a time axis error [- to extract the time axis error horizontally, and applies it to the time axis control means to include it in the input television signal. In the time axis error correcting device for removing a time axis error, the time axis control means includes a time axis control memory capable of controlling the input output in clock units, a shift register capable of controlling the time axis in clock units, and a clock pulse position.・Sampling means for applying a phase corresponding to the phase to the input No. 16, and by the reference signal of the horizontal scanning period separated from the accounting television polarization code and the reference horizontal scanning period signal, respectively Ij+J It: 1 of the memory In addition to performing readout and readout control, the previous m
2) controls the sampling means with a modulated clock signal obtained by controlling a shift register and further applying phase modulation to a clock signal of a constant cycle and phase according to a time axis error within one clock cycle; This feature is characterized by correcting the time axis of. The full details of the present invention will be elucidated below with reference to the drawings. Basics of time axis error correction in a time axis correction device yi) J
17, the time axis error of the input video signal detected by the above-mentioned operating principle is compared with the horizontal scanning period [H], and the time axis error is large enough to be discussed in 1~, and the clock period corresponding to the pixel period is The time axis HkM is divided into eight stages, each having a size of several clock cycles and a small time axis error less than the clock cycle, and the time axis error of each stage is corrected as follows. . (1) Horizontal 101 in input video No. 1 such as tape H
By detecting period I W and resetting the time axis □ correction system each time the tape H is removed, the time axis error, which is unacceptably large compared to the horizontal scanning period H, can be roughly corrected. to correct. (2) Based on the operating principle of time axis error detection according to the present invention as described above, using the standard clock signal for readout, and using the detected tape H etc. as a reference, the sine waveform of colorverse) fff or a predetermined low frequency band is detected. Detected by sampling a known input No. 1a waveform, such as a horizontal synchronization pulse waveform that has been modified due to its characteristics, and comparing the sample phase with a predetermined phase based on the standard/method] A time axis error as large as a clock cycle is corrected in units of clock cycles using a -1 variable delay by a shift register. (3) The small time axis difference that remains after the correction in steps (1) and (2) above and is less than the lock period,
For example, when performing time axis correction in the form of a gauge digital video signal, digital 16 coding, an A-D converter that performs sampling functions for the time axis used for analog signal ratio, and a D-A converter are used. When the timing of the driving clock signal remains in the device, etc., the error in one axis is 16%.
However, it is corrected by appropriately adjusting the IA using . As mentioned above, the time axis correction of the video signal according to the present invention can be performed according to the in-house standard without using a clock signal that locks the entire circuit system to the tape H. Driven by a clock signal, etc., it can be performed extremely quickly and accurately.Therefore, if the video signal to be corrected is also a gain signal, not only the control for time axis correction but also the video signal to be corrected can be digitalized. An example of the circuit configuration of the IMI axis correction device according to the present invention is shown in FIG. An input video signal such as a VTB playback signal is sampled by a sampling clock signal of a pixel period from a clock generator 15 (7) to form a DigiMole video old +-j 17, a video (8) slow daughter unit 2 and The synchronization separation circuit 9 separates and extracts the input horizontal synchronization signal from the tape H, etc. (7 supplies it to the burst flag generator 10.
〜, Generates a timing reference and a burst flag for time error detection based on the operating principle described in 1〜 above,
It is supplied to the time axis error detector 6. The time axis error signal detected by the time axis error detector 6 as described in detail based on the above-mentioned operating principle is divided into a large error component in units of a sampling clock period and a small error component in units of one sampling clock period or less. So, the former is the starting point? ti controller 11v ((↓(), and also supplies it to the latter all-clock phase modulator 7. Therefore, to correct a large time axis error in units of sampling clock cycles, the digital video @ signal mentioned above is sent to the shift register. supplied to (
Variable speed by taking out from 7 continuous shift steps! Although it is possible to perform correction by applying A, as in the configuration example shown in Figure 1, the starting point of the gauge digital image No. 1 for the time axis correction memory is limited depending on the size of the time axis error. By doing so, it is possible to perform equivalent correction even if the tape H or the like is subjected to a change delay 17. It should be noted that the tape any 11-'l! driven by the xanopring clock doubling clock from the clock generator 615. The correction f: 414 is the time error total compensation by the time axis error detection in the - axis error detector 6 1-11 After the Saitama axis error is detected, 11
This is a raw tape H complete book (Hemi start point system @ j device l) that cannot be done manually. 1. The configuration example shown in 11/1 is the same even if other b'' ~~ changes are made that will be described later. Or, since the entire circuit system is digitalized, each component of the digital circuit is tttll of the sunblink clock from the clock generation 5t5, as shown in FIG. 7J.
? As for operating under wholesale, we will omit the detailed explanation. On the other hand, -1 in Hozo Slow Gogo 2, Digital Hozo 1i
V(
- The digital video image is appropriately delayed, and the time side [difference detection ζi (
(According to 11j) Compensating for the time delay in detecting the axial difference difference - 2) Item 1! Yes, there it is, memory city 11 prefix 12, 1 included Start point controller 11, reset the memory 80 route address by the Matsukomi start point controller 11, memory; 3 () fabric VCkl, always horizontal blanking) A direct sliding component is written at the same timing between iJ1, and hereafter, the 11th and next L
With the increase in the number of write addresses such as Mi area, 2 area area, etc., memory addresses and digital image information
17 minutes water, 1/- timing 1i1f? There is a one-to-one correspondence.
Fl, ft% output for El (2 start points: 1i
ll side: 'il 18 K from the station (prefecture water 3 copy:
The motion pulse Hl) is delayed to 4 seconds, and the time is January 11th, so that the output video 1 - 2 is in line with the 4th line Hi = f number of the internal rotation board. 7 things? Kicking start city 11 plow A, I and 1. - By applying the voltage to the memory 8, VC1's φL output 17 stars (similar to 2+ of 1 crisis) is reset to the read address of 8 by the bow, and the () address of memory 3 is set. In order from 1: & Pond, 2nd place, 3rd” 1! I, and the total image bM of the bladder f:tj 1-C. moreover,
The clock phase 'X gain 8 is the time (I11
13 output glaze 1; Clock generator] II7' (1 (
IT"I degree] 1. By phase modulating the sampling clock doubled by its time 4!llll error component,
Approximately corrected the 1st axis of the left axis (-Digital image color, VC remaining box, 1st link clock period or less, timing side 1 error that matched the treetop Hf; working clock 16 arms) ... form timing circuit 4 and -
I-input to analog converter 5. deer[
7, since the clock that drives the digital analog converter 5 is phase modulated, the timing circuit 4 changes the digital lJ! according to this phase variation. J Hakuya No. 11 is a fully delayed IL, and there is no need for Kozue to be slow + J deaf, and the Tishitaru analog converter is used to convert the image to 1st speed 11.
+'j' is mislatched 1. It is okay if there is no. As described above, the output of the digital analog converter 5 is taken out at the outputs of the Kuramoto Mitsuaki 1jjJ and 1111 correction outputs of the sleeve correction device. In the +S configuration example shown in Figure 1, V, the following circuit operation □
The time axis error was corrected to almost the original value, and the time axis was adjusted to 14 by arbitrarily mixing and switching with other television f:image double-numbers under the control of the in-station standard synchronous board. 1
Supplementary IB output video information can be reported. 1- Therefore, in the configuration example shown in the first diagram,-1, the time axis error of the input video signal is divided into a large error component whose unit is a sampling clock period and a small error component which is less than 1' ring ring clock period. and 10 divisions (7) The former is corrected by adjusting the timing of output from all shift registers by adjusting the VCg14, and the latter correction is made by driving the digital analog converter that takes out the corrected output signal. As a clock false signal, the clock signal is locked to the internal standard Lfl (7), and a phase variation corresponding to the time error is given to the clock signal. Sampling is not arranged vertically (iii), so it is configured in a digital circuit (
21 At the time of this invention, the correction output of the tlI4\II sleeve correction device is directly taken out in the form of digital video 1g]7. In the case of supplying 1 unit (1 unit) in the form of Correction of small time axis error components less than the sampling clock period,
As in the configuration example shown in the lower part of FIG. 1, the above-mentioned correction is not performed in the digital-to-analog converter 5 on the output side, but in the human-powered analog-to-digital converter 1 prior to correction of the large time axis error component. + i + g As mentioned above, small time axis error correction of less than one sampling clock period
In addition, in the A unit, feed forward system @ + yc
According to the present invention, +h+ 11η11
What is the circuit configuration of the correction device? l] is shown in FIG. However, since most of the configuration example shown in the lower part of Figure 2 is the same as the configuration example shown in Figure 16, explanation of the circuit operation [ψ] is omitted. The major difference between the configuration example shown in the second diagram and the configuration example shown in the first diagram is that two analog-to-digital converters 1 and 1' are also provided on the input side. . [7 Then, one analog-to-digital converter 1 is
It is operated by a sampling clock signal from a clock generator 15 that is phase-synchronized with the internal standard clock signal,
1. Supplying the converted output digital video signal to the synchronous S divider 9. 1. Separation and extraction of input horizontal synchronizing signals from tape H, etc. used for time axis error detection according to the operating principle of the present invention.
The configuration is the same as in the configuration example shown in the first diagram (as in Sakae).
1ζ, the time axis error is large error component in units of total sampling clock period, and 1. It is divided into small error components less than or equal to the sampling clock cycle (7, the front edge is corrected using a variable delay by a shift register, and 7 is the same as in the configuration example shown in the first figure. 7111~ However, the latter is different from the configuration example shown in Figure 1 in that the time axis error [117/7] is smaller than one sampling clock period.The correction is performed by the input side ablog digital converter 1'. .<Difference] 7
ing. That is, this analog-to-digital converter 1
In ', the curved axis error is corrected when it is smaller than the sampling clock period.
A timing circuit 4 prior to the image j-y controller 2 similar to that in the illustrated configuration. Supply to 1. ing. In the timing circuit 4, in order to synchronize the digital image signal with the timing of the station standard clock (g), which is locked to the station standard synchronization signal, a circuit OT similar to that in the configuration example shown in Figure 1 is used to synchronize [T3]. As a result, the digital input video signal matches the internal standard clock signal, so writing to memory and starting can both be performed at the timing of the internal standard clock signal. , the clock that drives the digital analog converter 5 is also an internal standard clock signal, and the clock F+ shown in the first diagram is
! The time-base corrected output image signal, which has been subjected to the same large time-base error correction as in the example, has already been subjected to the problem (2 and M) before being supplied to the digital analog converter 5. There is no unevenness in the vertical direction of the knob ring structure, and the digital image can be directly supplied to other digital video equipment. As mentioned above, two analog-to-digital converters l and 1' were used on the input side, but of these, the analog-to-digital converter l was used exclusively for detecting time axis errors; analog =
The digital converter 1' is used exclusively for correcting minute time Q (4 errors). However, the detection of the time axis difference ends within the horizontal blanking period as described later, whereas the time Since the correction of the ftJIll1b error is performed only during the video period, if we pay attention to this point and use the switching between the horizontal plankinder jυ] and the video period, we get the following:
For example, the number of ffJ examples shown in FIG. 2 can be reduced to only one analog digital conversion function on the input side. That is, one analog-to-digital converter is installed on the input side, and an internal standard clock signal from the clock generator 15 is supplied during the horizontal blanking period during which time axis error detection is performed as described below. 1-11, time +11i It is possible to use it by supplying a phase modulated sampling clock signal from the clock phase converter 8 during the video period during which error correction is performed. FIG. 8 shows an example of the configuration of the time axis correction device of the present invention, in which the circuit configuration has been changed as described above. The configuration example shown in FIG. 8 has the same configuration as the configuration example shown in FIG. 17, a time axis error switch 18, and a clock switching flt controller 16 are additionally provided, and in the clock switch 17,
The sampling clock signal supplied to the analog-i-digital converter 1 and the timing circuit 4 is the local sampling clock signal from the clock generator 15 during the horizontal blanking period, and the sampling clock signal supplied to the analog-to-digital converter 1 and the timing circuit 4 is the internal sampling clock signal from the clock generator 15 during the horizontal blanking period. At t7, the clock is switched so that the phase modulation signal (201) is used as a pulling clock signal. On the other hand, in the time axis error switch 18, during the horizontal blanking period, the timing circuit 4 inputs the pixel timing correction signal. The time axis eye difference A6 component supplied in step 17 is set to zero, and the error switching is performed so that the above-mentioned minute time axis error component is used in the video period (at time IVI I11), and further V , in the clock switching controller 16, a horizontal blanking signal 113 is formed from the horizontal synchronizing signal of the input image year number such as tape H, and a signal J'□ switching fti control signal is generated to perform the above-mentioned switching. A signal is applied to each switch 17 and 18.Next, each structure commonly used in the configuration example of the time axis correction device of the present invention shown in FIGS. The time axis error detector 6 will be explained in detail below.As mentioned above, the operating principle of time axis error detection according to the present invention is as follows: Based on the predetermined phase relationship that exists at −1 between the station number and the local standard clock number,
The human-powered video signal is sampled using an in-house standard clock (MM), and the sample phase and ni
Calculate the time axis difference of the input video signal based on the deviation from the constant phase: l! ! It is based on the same operating principle as the decoding of color signals when receiving standard television video signals.
(The input horizontal synchronizing signal of [2〈] is a known predetermined signal waveform in the input video ' signal waveform based on the burst flag No. 1B, which is formed by applying a certain delay to the horizontal synchronizing signal (1-). ], 2. Calculate the two signal components that should maintain a mutually orthogonal phase relationship [7. Take the ratio of the two orthogonal components and calculate the inverse JI1..Total 1..2, its arctangent fi'# of tape H, the sampling phase angle is determined based on the input horizontal open M signal of tape H, etc., and by converting the sampling phase angle into a time product,
Based on input horizontal and synchronizing signals such as 7, etc., a time-axis image difference that can be recognized to be almost maintained even in the subsequent image period is quickly detected without any continuation within the horizontal blanking period. It was designed so that Based on this operating principle, the standard clock signal...
7D "When a colored signal sound is used as a previously published signal waveform □ which should have a fixed phase relationship (an example of the mode of time axis error detection according to the present invention in an IC is shown in figure m4. The colorverse H signal waveform is an example when the frequency of the standard clock signal is four times the color burst frequency, and in the illustrated example, one cycle of the sine waveform forming the color burst signal is Sampling is performed at 4 points, and each sample level is xl n l XB n
Let T XB n l X4 n. Note that the subscript n indicates that the nth and lth sine wave in the color burst signal is sampled. Therefore, if the amplitude of the color burst signal is A, its itt flow level is iB]7, and the phase at the sampling point of the sample level X1n is θ, then the above-mentioned valley sample level at each sampling point is as follows. It is expressed as Xl n =B+ASinθ
niX,! 11 =B0As1n(θ+90°)
=B+Acosθ (2)XB H=B 10A 5
in(θ+180°1”B-ASinθ (8)...
x=B+ASin(θ+270°)=B-Ac
os θ (4)4. n Here, the phases must be exactly opposite to each other'I! ! The difference between the two Zanglerehers, tfc, that is,
) and the difference between X2n(2) and X4n(4) are as follows. X1. n Xs, n = 21 S1n
θ (5)X, n-X4. n=
2ACO8θ (6) such sample level difference (5), (6) ′(il- color burst for the whole issue, or for the transient phenomenon! Hibiki 7 &: central part with both rear ends discarded after siJ to remove If we integrate each of the color burst toggle numbers, we can obtain two components whose phases are orthogonal to each other as follows. ■・ = Σ'(x −X ) (7) S
In n 1 , n 8+”, the orthogonal two-component process, □ n (7) and process ..6 (8) are taken to calculate the arctangent, and the sampling for the color burst signal 1 z4 1 waveform shown in the figure is obtained. The phase angle, that is, □time axis error can be calculated.In addition, when the sample phase θ at the earliest sampling point mentioned above is θ=O, the time axis error is zero, and such time axis Assuming that the range of values in which the sample phase θ can change is from -180° to +180° with the state of zero error as the center, the sampling phase angle of the color burst signal expressed by this earliest sample phase θ is as follows. To convert this sampling phase angle to [inter-call ratio],
Since the color burst frequency is 174, which is the standard clock wave number, a phase angle of 90° is considered to be 1 clock cycle, and 1~
Therefore, it is possible to detect the time axis error in the time shift range corresponding to ±2 clock cycles using equation (9). Target and 17.
25. An example of the configuration of a time axis error detector according to the present invention is shown in FIG. In the illustrated configuration example,
The shift register 19'fr is driven by the internal standard clock No. 17 and is supplied to the shift register 19 in series (the input digital image color is taken out in parallel at the phase interval of the clock cycle, -1~20-
4, input colorverse) (4-phase gain/tal image level 1M number X1.n l St, obtained for four sampling points for each cycle of N number)
n l 8. n l 4. n is repeatedly extracted over a cycle period. The sample phase data for multiple cycles are led to the subtracter 21-1.21-2, and the obtained subtracted output is added to the combination of 522-1.22-2 and the D flip-flop 28-1.23-2. 1 constructed by
It is supplied to a pair of integrators and subjected to integration according to the above-mentioned equations (7) and (8), and the integrated value is sent to a pair of latch circuits 24.
-1°24-2. The pair of latch circuits 24
-1. , 24-2, the burst flag pulse, which has been appropriately formed to have a pulse width corresponding to at least the central multiple cycle period of the color burst signal in the human image signal, is externally subjected to edge inspection. The above-mentioned integral value is latched at the trailing edge of the burst flag pulse detected by the detector 26 and the trailing edge detector 527, and then outputted to the orthogonal two-component signal [7] , according to the above equation (9), extract the arctangent of the orthogonal two-component signal and the time axis error signal. Note that the leading edge pulse of the burst flag pulse detected by the leading edge detector 26 described above is cleared every horizontal scanning period of the D free lag flop 23-1°23-2i that constitutes the above-mentioned 1...integrator. At the same time, the standard internal clock 15 is divided by -17 and reset at the color subcarrier wave number, that is, the frequency of the color burst signal, and each D clip frog 20-1 to 20-4 and 2s-1, 23-2'fiIXl! The above-mentioned one clock signal with 1=71 is generated. Further, the reverse check connector 25 is, for example, -L within a range that can actually occur. (Also, it is possible to store in advance the arctangent value corresponding to any f[↓ combination of self-father binary components and [g], or to easily configure it using a one-domain memory IJ ROM. 1. As mentioned above, the known f in the input image signal
1 of the relative phase between the No. 8 waveform and the local standard clock signal
When detecting the time axis error based on the deviation from the positive M value, that is, the phase error, if the input image signal contains a color burst signal, the color burst signal is detected as described above. It is preferable to perform time axis error detection according to the present invention as . However, when color burst No. 16 is not present in the input image signal, the 11r phase error similar to that described above for the ↑ moon waveform of the horizontal synchronizing pulse such as tape H will occur. Time axis error detection can also be performed, and this is an aspect of phase eye difference detection in such a case. Examples are shown in FIGS. 6(a) to 6(0). The curve shown is only the rising portion of the horizontal synchronizing pulse, which has been properly trenched by guiding the input image No. 6 to a low-pass filter with a known predetermined passband characteristic and giving it a predetermined slope. 7, and such signal waveforms are standard. (28) When sampled with a sampling clock whose phase is synchronized with the lock signal, if the time axis error of input image No. 48 with respect to the internal standard clock signal is zero, as shown in FIG. Assume that the horizontal pulse is scaled so that the sampling point is approximately located on the slope part of the rising signal waveform. That is, the sample level 2 at the 8 sampling points + rectangular Kx, , x2. x8 and ( -, in the case of a time axis converter, the second sunblink point indicating the level x2f is located at the center of the slope as shown in Figure (a). '(r-H).[7] Then, the ratio R of the sample level difference between the IIA contact point and the IIA contact point for the three sampling points is given by x2-x. If converted into iVC, it is possible to obtain the 1111 axis error for the input image signal as in the previous example, and as shown in Figure 6(a), it is always 8 x 7'.
The level difference between the IJ and D points is equal, and R=] ・(2
9) Then, the time axis error becomes zero, and in the same figure (b), □
As shown, x8-x2> x2- x, so R>1
When , the phase is advanced, and as shown in the same figure (○), Xs
When X2<X2-X, and R<1, a time axis error can be extracted as a delayed phase. FIG. 7 shows an example of the configuration of the time III error detector according to the present invention, which targets all the horizontal synchronizing pulses in the input image burst as described above. In the illustrated configuration, when 11j1
] The input digital image signal whose error is to be detected is
Low-pass filter 2 f with constant ir passband characteristics
), the horizontal synchronous pulse wave engraving is made 1 with a predetermined inclination as described above, and then the signal is supplied in series to the shift register 19, and the three sample levels described above with reference to FIG. 6 are taken out in parallel 7. teras□su [! 1111f62
4-1 to 24-8 [7, taken out at an appropriate timing by the synchronization separator 9 and the tape H slow sharpener 14 (after being latched once at the trailing edge of the horizontal synchronization pulse of the tape H, etc.) The above-mentioned (1,0
), calculate the ratio R of the sample level difference by (1)□,
Furthermore, the time axis error is calculated by converting it into time ', -. Note that, like the arctangent unit 25 in the configuration example of sit J'ls, this time axis converter 30 can be easily configured using a read-only memory that stores required data. 1) Separate and extract the horizontal synchronizing pulse of tape H etc. from the input image signal a) The deep H delay sharpener 14 in the circuit system detects the low frequency of the input image signal targeted for axis error detection. g', which serves to compensate for the time delay caused by the pass filter 29, is then used for detection 1. as described above. The mode of time axis correction VC applied to input image 1B based on the time axis error will be described below. il, iI in units of sampling clock period
Regarding correction of extremely large time axis errors, a convolution start point of 7.4 is stored in the memory device 117 to correct the time axis of the input image 1 by adjusting the timing of 1 inclusion 1 and bladder ejection. This can be achieved by applying a variable delay depending on the magnitude of the time-11 error component in units of clock cycles.
□Example of l-, fcM path configuration to perform all packing III
It is shown in FIG. In the illustrated circuit configuration, the human-powered horizontal synchronizing pulse train of the deep H temple is automatically supplied to the shift register 19, and the data selector 31 is connected in parallel to the intermediate stage at one sampling clock interval in the shift register 19.
Continuing to this (~, among the delay pulses written from those intermediate stages, the intermediate delay 'AM' is the center of the delay pulse I.
F timing (7) A slow st pulse with timing correction of the lean flinder clock dark period unit within an appropriate delay range ('□);
■ Selectively extract. 1j when it is less than one sampling clock period
i 111111 The correction of the error is as described above (7) in Fig. 1 to Fig. 3 in the time axis correction device of the present invention.
This is preferably done by an analog-to-digital converter with a single input or a digital-to-analog converter on the output side; in either case, the clock signal driving the converter, in particular the sampling clock, should be corrected. This is achieved by applying phase modulation to the minute time axis error component according to (82). Examples of the structure of such a clock phase modulator 8 are shown in FIGS. 9 to 11. Note that in both the illustrated examples, the minute time axis error component of time −%j smaller than the sampler clock period is calculated by 4.
The circuit configuration in □ is obtained when binarizing with bits, but the number of bits is set arbitrarily and the minute time axis error component is reduced to 2 bits per series, t, m. It goes without saying that it is something that 1. In the example shown in FIG. 9, the clock phase modulator 8 is configured in parallel, and the clock phase modulator 8 is divided into 16 equal parts of the total lock period.
Tarock delay elements 38-1 to 83-15 are all connected in series, and each clock M! Intermediate taps are provided at each of the input and output terminals of the reef, and connected in parallel to the data selector 31, and the buffer amplifier 82 is supplied to the clock delay element multiplex circuit 83 through the buffer amplifier 82. A delay of equal to +iLt is applied to the clock signal, and then 11 delayed clocks of the standard clock period of 17 are connected in parallel to the data selector 8.
supply to. The data selector 3] contains 2 (i
M・L88) (Separately mark the above-mentioned imitation short time Tsukuda 1 difference component in +
-, , -(, □'), select a delayed clock signal having an amount of 1M or more corresponding to the error value, take out the shift, check the phase change, and use it as a lock signal. In this example, the clock phase modulator is configured in an 8-way array type, and the 111th order bit of the natural 2-tracing code with the same number of bits as the 21st code which covers minute time axis error components is Z. [7] Apply lumi t'1 ke to the middle bar, ``fc, shoulder the slow % bolt 411M
For example, data selectors 31-1 to 31-4 are connected sequentially after the clockers 86 in descending order of delay lids, so that the total delay lid by each delay element is equal to the sampling clock period. do. 1, and each bit of the minute time axis error component described by Ail, which is binary encoded with 4 bits and is 7, is applied to each data selector 8]. The standard frequency sungrind clock signal supplied to the series circuit of this configuration via 82 buffer amplifiers is
II 1lIl11 By the river selection operation of each data selector 31 according to the time 111 of the error component, j corresponds to the first-order bit, respectively] - through the valley lock slow learner, or, The short circuit (-7) is sequentially entered into the phase modulation clock signal and taken out as a phase modulated clock signal. Yes, - 8 clock delay elements 85-1-85-8k with linkage
Connect to the IQt column with 1- and 1□ with all intermediate taps of the input/output terminals.
and connected in parallel to the data selector 31-1 1. A similar configuration as the parallel type shown in FIG. 9 was constructed in the same manner as the parallel type shown in FIG. Configure a series-parallel circuit with vertical connections l~, and connect each data selector 3
According to the above-mentioned binary stamping imitation small time axis error component applied in parallel to I7') Hj control [7, the sampling clock No. A phase modulated clock signal 1 formed by applying a delay similar to that of the parallel type shown in FIG. 1 and the serial type shown in FIG. In the configuration example shown in FIG. 1 to FIG. 8, which is driven by the phase modulated clock signal formed as described above to correct the minute time axis error component mentioned above I7 contained in the input image signal. The timing circuit 4 may be placed in the digital-to-analog converter 5 or the analog-to-digital converter 1.1'.

[The code below is used to modify the timing of the digital image signal for each conversion input or conversion input, and to adjust the timing between the conversion input and output digital image signal and the internal 81 clock signal. FIG. 12 shows an example of the configuration of the timing circuit 4 that performs this function. In the illustrated configuration, two D flip-flops 2 (1-1 and 120-2
Insert the period 86 of the internal standard clock signal between
Alternatively, the data switch 87 that switches the connection to short-circuit between them is controlled by the uppermost pit signal of the binary encoded minute time axis error component (86), and each D flip-frog □20
-1 and 2o-22 are driven, respectively, to prevent the mistiming of the digital image (i) due to the difference in phase of the clock (l) and the clock (ilff). In the case where the correction of minute time 4III errors contained in the input image signal is performed by the digital-to-analog converter 5 on the output side, the clock signal 1 is set as the internal standard clock signal, and the clock signal 2 is set as the phase modulation clock. as a signal, and
As in the configuration example shown in Fig. 2 and Fig. a''□, the correction of the minute time axis error mentioned above is
In the case of digital transformers 1 and 1', the clock numbers 1 and 2 are reversed to those described above. Thus, each D flip-frog 20-1, 20-2' is supplied with an input digital image signal]7
If the input system and output system are latched by clocks 1 and 2, and the timing difference between them is severe, 87' 12, the digital images of the input system and output system, which are respectively operating with different clocks 1g, are displayed. Try to match the timing of the decoding. However, in the explanation so far, all corrections of time axis errors included in image signals are performed in the form of feedforward control, but feedback control is not limited to this example. Similarly, the time axis error correction can be performed in the same manner.An example of the configuration of the time axis correction device of the present invention in the case where such feedback control is performed is shown in FIG. 18.The illustrated example of the configuration In this case, in an overall configuration that is roughly similar to the configuration example shown in FIG. However, as is clear from the figure, this feedback loop does not function as a phase-locked loop PLL on the driving clock signal as in the conventional device.
All clock signals are clocked by clock generator 1.
5 to 1 are supplied independently from the loop connection [7 to 1], and are not subjected to any locking action. That is, although the configuration example shown in FIG. 18 is in the form of feedback control, it is similar to the basic configuration (7) to the configuration example shown in FIG. 8 or 2, and has a certain phase. Assume that there is a tarokk signal with a clock signal, and by sampling the input image signal using the clock signal, the child's time axis error is detected based on the operating principle of the present invention described above. , Fig. 8) “□ to 2nd
In the configuration example shown in the figure, the clock signal having a certain phase described above is the clock signal that drives the entire device, that is, the internal standard clock signal, and the time axis correction is performed based on the phase of this internal standard clock signal. Time axis correction is performed by subjecting the internal standard clock signal j to phase modulation corresponding to the time axis error. Thinking in the same way, a clock signal with a certain phase in the configuration example shown in Figure 18 means a clock signal that has a certain phase immediately before the current horizontal scanning period that is subject to time axis correction... The clock signal 4d samples the image signal □+5 in the scanning period, and the time axis error detection and correction performed by the clock signal 1H, which has been time-axis corrected, is based on the image signal (2) in the horizontal scanning period of rkntl.
H is sampled [Also, the time axis difference is detected as a reference for the entire phase of the clock signal, and the clock signal is phase modulated by the time axis error. Therefore, the time axis correction system used for time axis correction during the immediately preceding mizukohi running period? It is a good idea to add or subtract the 1-axis direct M of the above-mentioned 1 "time window detected in this way" to the current horizontal scanning period to the l141 eccentricity code, and such addition also reduces the time axis error due to j ~ 1. This is done by an integrator 38. In other words, there must be no time axis error in the image signal of the current water cycle.
Therefore, the time axis correction control number 1 used in the preceding horizontal fixing period can be used continuously without any changes.
Further, if the image signal of the current horizontal scanning period includes a time axis error, 1381til axis correction can be performed according to the time axis error. (40) 1. As shown in Figures 1 to 3 and Figure 18,
In addition, in the configuration examples of the time axis correction device of the present invention, at the beginning of the sequential horizontal scanning period of the human-powered image signal and during the horizontal erasing period, the colorverse) (ff1 is also [7 After detecting and correcting the time axis error using the reference signal as a reference signal, it is assumed that there is almost no change in the temporal eye difference even in the subsequent image period [...] The state of the time axis correction that has been changed is maintained at -f-F during the seven horizontal scanning periods, and for example, due to a constant deviation in the tape speed of V"" The so-called speed error correction that corrects the continuous 1. direct expansion change of the time axis error lid while ignoring 1iJ+axis error change +-1L when it occurs linearly has been omitted, but It goes without saying that the speed error correction for correcting the change in error during the image period can also be used in conjunction with the time axis correction described in 11. FIG. 14 shows an example of the configuration of the main parts of the time axis correction device of the present invention when such speed error correction is used in combination.
(41+ is shown. In the configuration of the main part shown, for example, the time □11
Detected by 11I error simulator 6 1. The horizontal synchronization signal in image No. 18 is also changed to 1. < is latched in response to the application of a related signal, e.g. Since the time axes at the beginning of each horizontal scanning period appear at the same time, their time 111 errors are supplied to the interpolation circuit 41.
The weight is changed along the if line, and direct fat interpolation is applied between all the clocks. The phase modulated clock signal is then applied to the timing circuit 4 and the digital-1 analog! -1+ unit 5 is supplied. In addition,
The input digital image signals sequentially supplied to the timing circuit 4 and the digital-to-analog converter are supplied via an IH delay line 40 for compensating for the time delay caused by the interpolation circuit 41. In addition, the speed error correction circuit C configured as shown in the figure is inserted immediately before the digital-to-analog converter on the output side in any of the configurations of the present invention apparatus. In the configuration example, two systems are connected in cascade to the clock phase modulator 8 and the timing circuit 4 (I) to both the time axis tracking correction described in 7 and the speed error correction described in 17 above.
It is also possible to share both the clock phase modulator 8 and the timing circuit 4, respectively. As is clear from the above description, according to the present invention, it is possible to obtain
Input 11 of image signals, etc. played back from a VTR! ii fl
! Conventionally, the error in the axis between the 4-signal signals was corrected by differentiating the timing of the p-p-k 16 used for inserting and inserting the memory element.
Only the internal standard clock signal for readout is subjected to the same time axis error correction, so the convolution clock (No. 8 and the horizontal synchronization signal of the input image signal of tape 'H@-) without requiring time for phase synchronization.
If the input horizontal synchronization clock signal of Chive H, etc. is detected, the time error is detected and corrected immediately without delay, and an appropriate time axis that is phase-synchronized with the station internal clock signal is detected. It is possible to quickly and accurately obtain image signals for curing patients. In other words, since the clock signal from the coaxial source is commonly used for the clock signal for loading the main element for time axis correction and the clock signal for ejecting the bladder, memory control is easy with 4 W). At the same time, the signal processing within the device is controlled by those clocks 1L! $! Since the signal is sampled, it is possible to perform all digital processing, and therefore, it is possible to easily boast of extremely high accuracy and fidelity. In particular, the detection of the time axis difference according to the operating principle of the present invention used in the configuration example shown in FIG. Accumulation] 7. This provides the advantage that the straight running detection can be carried out reliably. As described above, the time axis correction device of the present invention has an extremely fast response speed to the correction of time axis errors, and is used for recording and reproducing high quality color preview signals. (44) It can be called a time i41+correction device used in combination with a VTR. In the luminance and color polarization recording and reproducing methods, even if a time axis error remains in the reproduced number, #, lI8 [remaining time errors in the reproduced image]做I1. in the horizontal direction. Although the residual time axis error of the reproduced color signal can be completely ignored since it appears as a pupil shift of about 1H, the reconnaissance color TV that multiplexes the bright colors and the bright colors. In the method of generating old autographs in the form of fine details of all of John's signals, the time axis error that exists in the reproduced color is 1%.
This appears as a phase rotation, that is, a shift in the color IJ phase, which deteriorates the Kiryu Cassie painting. Therefore, in the Ki If l6 bow/Iro 1 bo issue separated date record reproducing force formula, if the time axis correction according to this redundancy is applied, Ail
Although it is uneasy to use the speed change error correction described in 7.
In order to avoid deterioration before the endogenous color LljII due to the residual time axis error mentioned above (7), the Irokami Ai= method was originally intended to be used in conjunction with the product fsl color television short code record student VTR. 1. When wideband and high stability...1 dIll+Sleeve E (45・) The time axis correction device of the present invention #, T'
However, even when playing back a color television using the current standard method, color images using the brightness/color selection method (as far as i!M is concerned, the residual time axis error is It is necessary to use speed difference correction in order to reduce the speed difference.In addition, the +Al axis correction device according to the present invention can be used not only for the above-mentioned reproduced image from the VTR, but also for video Appropriate changes can also be made to the synchronizer, etc. to achieve the same effect. 4. Brief description of the drawings Figure 1 shows an example of the configuration of the time axis correction device of the present invention. FIG. 2 is a block diagram showing another example of the configuration; FIG. 3 is a block diagram showing another example of the 1rtl configuration; FIG. 4 is a time axis diagram according to the present invention. 18 showing the mode of error detection
Figure 5 is a block diagram showing a configuration example of the time axis error detector according to the present invention, Figures 6 (a), (b), and (c) are diagrams showing other examples of the time axis error detection according to the present invention. I-d waveform diagram showing the aspects sequentially,
FIG. 7 is a block diagram showing another configuration example of the time 11QII error detection Lb device according to the present invention, and FIG. 8 is a block diagram showing a configuration example of the memory loading start point controller according to the present invention. Figure 9 shows the clock phase variation tJ, IJ according to the present invention.
FIG. 10 is a block diagram showing another example of the structure; FIG. 11 is a block diagram showing another example of the structure; FIG. 12 is a timing diagram according to the present invention. FIG. 13 is a block diagram showing another example of the configuration of the time axis correction device of the present invention; FIG. 14 is a block diagram showing an example of the configuration of the speed error correction device of the present invention. It is a line diagram.・ ], 1' Analog-to-digital converter, 2/Video 1 video delay converter, 2 (memory element, 4 Timing circuit, 5
Digital-to-analog converter, +3 Time axis error detection 4if, 7 - Time axis error delay device, 8 - Clock phase modulator, 9 - Synchronization separator, 10 Burst flag generator, 11 - Coordination start point controller, 12・Memory control unit 1, 13... Front start switch, itf controller, ], -1, Tape H delay unit, 15 ・Clock generator, 16 Clock switching controller, 17 Cronk cutter, 18 Time axis error switch, 197 note register,
20.20-1~20-4.28゜23-1.28-2
・D flip frog, 21° 21-L, 21-2...
Reducing scooper, 22.22-1゜22-2... Adding scooper, 24
1.24-1 to 24-3 Latch circuit, 25 Arctangent, 26 Leading edge detector, 1-pass filter, 30 Time axis converter, 31. 31-1 to 31-4 Data selector, 32 ...Buffer (48) 87..Data switch, 3rd..Integrator, 39.Tape H position modulator, 410.LH delay device, 41..Interpolation circuit. Takei “Applicant: Japan Broadcasting Association (49)

Claims (1)

[Scope of Claims] 1. A time axis correction device that corrects the time axis of a human-powered image signal to form an output image signal having a reference time axis,
the correlation between a plurality of sample values each sampled by a sampling clock signal having the reference time axis in a reference signal waveform of a horizontal foot eclipse period associated with the input image signal and the output image signal, respectively; time axis error detection means for detecting all time axis errors of the time axis of the input image signal with respect to the reference time axis based on the deviation between the input image signal and the output image signal; and the sampled input image; a memory means for controlling a time interval between writing and retrieval of a signal according to a dog time axis error component of the time axis error having a time amount that is an integral multiple of the period of the sampling clock signal; The reference clock signal having the reference time axis is phase-modulated according to a small time-axis error component having a time amount smaller than the period of the sampling clock signal among the time-axis errors (7). clock phase modulation means for forming a signal;
Preferably, the input image signal written to or read from the memory means is sampled by the phase modulation clock signal, and the input image No. 11 read from the memory means is used as the output image signal. A time axis correction device featuring: M. The time axis correction device according to claim 1, wherein the bIS reference signal waveform is a color burst waveform. 8. The time base correction device according to claim 1, wherein the reference signal waveform is a horizontal synchronization one-word waveform. 4. In the time axis correction device according to claim 1, 2, or 3, N! The sampled input image signal is converted into a coded image signal, and the digital-analog converter for decoding the coded image signal reads out the input image signal from the memory means using the phase modulation clock signal. A time axis correction device characterized by sampling. (5) The time axis correction device according to claim 1, 2, or 8 converts the sampled input image signal into an encoded image signal and encodes the input image signal. A time axis correction device characterized in that the input image signal written in the memory means is sampled by the atto-nalog digital converter using the phase modulation clock signal.