JPS5812424A - Sequential comparison type a/d converter - Google Patents

Abstract

PURPOSE:To eliminate the need for a D/A converter composed of a resistance network, and to facilitate integration, by performing A/D conversion through the charging and discharging of a capacitor. CONSTITUTION:The plus terminal of an integrator A composed of an operational amplifier 1 and a capacitor C3 is grounded, and its output is connected to the minus terminal of a comparator 2. The negative electrode of a reference voltage source 4 is connected to the minus terminal of the amplifier 1 through switches S1 and S2 and a capacitor C2. Further, a capacitor C1 grounded at one terminal is connected between the switches S1 and S2, and switches S3-S5 are connected in parallel to the capacitors C1 and C3. Input voltages applied to the plus terminal of the comparator 2 are converted successively into digital values by operating the switches S1-S5. Thus, the A/D conversion utilizes the charging and discharging of the capacitors, so the need for a D/A converter composed of a resistance network is eliminated, facilitating integration.

Description

[Detailed description of the invention] This book concerns the coupled comparative Sum/D transformation 1) K.

A D/mu converter is usually used for the iterative comparison/D conversion.
t 6 D/MU exchange S is a precise resistance KII strategy t!
Since it is used as a La quasi-voltage source and only this resistor network has to be fabricated in a separate semiconductor process, it has the drawback of increasing the number of 11 crystals and increasing the manufacturing cost.

Honll beak Henji JkIIA! The 1M/D converter uses a number/D converter from a resistor-path network such as 1D. There are 14 photographs provided.

Hereinafter, the first part about the 011th ratio/D* exchanger of the present invention will be explained.
A detailed explanation will be given with reference to one embodiment of the figure.

■Km, Furusan Kohata Yu 1 and Tomi Denna 0 Hatakara Banzumi Hidekimu and Oni Shun @! Compare with the output terminal of the integrator.
The input terminal of I2 is connected to 1, the member electrode of Tsurugame Voltage 114 is connected to one end of switch 114, and the other end is connected to switch 1F? l! , , II4 expansion bond ys 0. At one end of each of them, randy yto.

and switch S, the other ends of which are grounded, and switch 8. is connected to the other end of switch 8°. and one end of the conduit CI,
Sui v? The other end of the B Tatsubi Hatake capacitor C is the calculation increase 111
It is connected to the jlc@ input terminal of No. 11.

Further, a switch Bs is connected between the input terminal and the output terminal of the operational amplifier. A non-inverting input terminal of the operational amplifier 1 is connected to ground 1. An input voltage v8 is applied from the non-inverting input terminal S of the comparator 2.

The terminal S is connected to the W-V circuit, the input voltage M8 is digitally converted, and the charge capacities of the capacitors C3a, , C, are equal, and the switch V f8, ~8.11M0!
! ) Semiconductor switches such as Thungista.

In the following, an explanation will be given of an embodiment of the invention.

First, the switches S, S, and S are turned on, and a reference voltage is applied from the voltage source 4 to the capacitor C and the IC to charge the capacitor. Capacitor 0. The mockery of Sengen Denshin Ma□ is Ichima Tomi de Ban (Ma, - Ichima 1).

The voltage between the terminals of the capacitors C, , a, el#Ll is zero, and e) s (V・proverb @ Lulu O). Also, from the above state, S, , a, , S , and then turn on the switch s, the charge of ndenna C1 (c1
・V, ) is the capacitor C1, and the charge of the conduit y-to- is that house! Conde/lo・ has 4@Toru 1, so C sophistication・
Mag 8 layers a, V,.

Compare ζQ and the output voltage of the integrator M@hatona1゜a><IC output voltage M, and -2's *cross-view input terminal 191 input to the 191 human power electric box! Comparison 1) and 2. For aA power voltage ma, ma3〉ma, and Ii, turn off switch S and then switch ♂.

Discharge the charge of ylcL''C and y9 ol 1 豐 8 Then turn on the switch 84 KL, [from sui V?ε tyK, the charge of cond y 0 嘗 is 13/zunona C
The voltage across the terminals of s1c is distributed between the voltage between the terminals of s1c and the voltage between the terminals of capacitor C1. Open force voltage)! 7,
87 ma, +-iv, ÷V.

If I x < MA0, turn off switch 8, turn on switch 8.
1 is discharged. After that, switch S is turned off, and then switch 8. When turned on, capacitor CI
Is the charge of condenser? Distribute to C1, :yndenna C
, , C, is k as shown in the following equation).

Ma,, bite,, Takashiyu V.

The output power EVe is Ma, wealth (ma, -1 ma ÷ ma).

In this way, the above operations are repeated depending on the magnitude of k, input voltage ma, and output voltage ma to perform the M/D invitation.

The coupled comparison type M/D conversion S of the present invention is a switch S.

This is a method in which the input voltage is sequentially changed digitally by manipulating the electric charge charged in the capacitor by manipulating 8I. As mentioned above, by charging and discharging the capacitor, the
Since it is a D conversion method, it is possible to prevent harmful birds by forming a '3/D/F association in the manufacturing process of the M08 Totsunzister, so by configuring the semiconductor switch and capacitor on the same board, it is possible to create a tortoise integration circuit.
It is extremely effective.

Also, as a feature on ms, one end of Koyden tC1)!
Also, since one end of the capacitors O, C, is connected to the input terminal of the operational amplifier 1 and is grounded in terms of grounding, there is no conversion difference due to grounding capacitance. have.

[Brief explanation of the drawing]

FIG. 1 shows an embodiment of a first-order ratio/D converter according to the present invention. 1g operation integrator, 1g calculation integrator. 2+ Comparator patent applicant Toko Co., Ltd. Kinsha

Claims (1)

[Claims] an integrator consisting of a first comparator and an operational amplifier, and a comparator, an output terminal of the integrator being connected to an input terminal of the comparator, and a first reference voltage; A first switch is connected to the negative voltage of the source, a second switch is connected to the other end of the first switch, the first switch and the second tundenna are connected, and the first switch and the second = The other end of the capacitor is grounded, the third capacitor and the fourth switch are connected to the other end of the second switch, and the other end of the third capacitor and the fourth switch is connected to # operation. A fifth switch is connected to the input terminal of the amplifier, and a fifth switch is opened between the summer input field and the output terminal of the arithmetic amplifier. A successive approximation fiA/D converter that discriminates input voltage.