JPS5812392A - Flattened wire - Google Patents
Flattened wireInfo
- Publication number
- JPS5812392A JPS5812392A JP10934081A JP10934081A JPS5812392A JP S5812392 A JPS5812392 A JP S5812392A JP 10934081 A JP10934081 A JP 10934081A JP 10934081 A JP10934081 A JP 10934081A JP S5812392 A JPS5812392 A JP S5812392A
- Authority
- JP
- Japan
- Prior art keywords
- wiring
- polymer resin
- flattened
- polymer
- resin film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Manufacturing Of Printed Wiring (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
本発明は平坦化配線に関し、更に詳述すれば、高分子樹
脂膜で導電層が形成されている平坦化配線に関するもの
である。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a planarized wiring, and more specifically, to a planarized wiring in which a conductive layer is formed of a polymer resin film.
従来、配線は、一般に銅やアルミニウムを蒸着し、配線
形状にエツチングして形成していた。たとえば、第1図
に示すように、樹脂基板上に配線を形成するには、基板
形成工程1.金属被着工程2、金属食刻のための配線マ
スク形成工程3.金属層のエッチング工程4.配線マス
クの除去工程5、が必要である。従って、工程数が多い
こと力島ら製造プストも高くなっていた。また、配線と
基板間には段差が生じ、導電体層を幾重にも絶縁体層を
介して積重ねる所謂多層配線を形成する場合には断線が
生じることもあつ九。Conventionally, wiring has generally been formed by vapor depositing copper or aluminum and etching it into the wiring shape. For example, as shown in FIG. 1, in order to form wiring on a resin substrate, substrate forming step 1. Metal deposition process 2, wiring mask formation process for metal etching 3. Etching process of metal layer 4. A wiring mask removal step 5 is required. Therefore, the cost of manufacturing Rikishima et al. was also high due to the large number of steps. In addition, there is a difference in level between the wiring and the board, and when a so-called multilayer wiring is formed in which multiple conductive layers are stacked with insulating layers interposed therebetween, disconnection may occur.
本発明の目的は、上記欠点の無い、製法が容易で、且つ
、電気的特性の良好な平坦化配線を提供することにある
。An object of the present invention is to provide a planarized wiring that does not have the above-mentioned drawbacks, is easy to manufacture, and has good electrical characteristics.
上記目的を達成するための本発明の構成は、高分子樹脂
からなる絶縁性基板に、選択的にレーザ光照射を行って
導体化された導電性高分子樹脂膜を擁することにある。The structure of the present invention for achieving the above object is to provide an insulating substrate made of a polymer resin with a conductive polymer resin film made conductive by selective laser beam irradiation.
ポリイミド、ポリアクリロニトリル、ボリアきトイミド
、フェノール樹脂、ポリフェニレン、ポリフェニレンス
ルフィド、ポリアセチレンなどの高分子樹脂は、通常の
状態で導電性が低く絶縁体として供されている。これら
高分子樹脂に、COlガスのCWレーザー光を照射させ
ると、照射された部分ではポリイミドから低分子(例え
ばHlo。Polymer resins such as polyimide, polyacrylonitrile, polyacrylic toimide, phenol resin, polyphenylene, polyphenylene sulfide, and polyacetylene have low conductivity in their normal state and are used as insulators. When these polymer resins are irradiated with a CW laser beam of COI gas, the irradiated portions change from polyimide to low molecules (for example, Hlo).
co、 co!など)の脱離反応を生じ、照射部分の高
分子は導電体化した。その導電率はレーザー光強度、走
査速度などによって所望の値を採シ得るが、通常の導体
配線に用いられる最大101Ω゛1・cW1′″1程度
までの導電率までは容易に得られる。また、レーザー光
の焦点の位置によっても導電率を調整し得るが、表面部
分に焦点を結ばせた場合には、導電体化した領域は、横
幅はレーザー光のスポット径40amであり、深さは5
〜10μmであり、好適である。Co, co! ), and the polymer in the irradiated area became a conductor. The conductivity can be set to a desired value depending on the laser beam intensity, scanning speed, etc., but it is easy to obtain a conductivity up to a maximum of about 101Ω゛1・cW1′″1, which is used for ordinary conductor wiring. The conductivity can also be adjusted by the position of the focal point of the laser beam, but when focusing on the surface part, the conductive area has a width of 40 am and a depth of 40 am. 5
~10 μm, which is suitable.
上記高分子樹脂は、予じめ、i、 # B’l e ”
4などのハロゲン分子、 A8F、などのルイス酸。The above-mentioned polymer resin is prepared in advance by i, #B'le''
Halogen molecules such as 4, Lewis acids such as A8F, etc.
1−6so、などのプロトン酸、Ll、Na、K など
のアルカリ金属をドープさせられたものであると、光照
射によシ更に導電率が向上するのでなおよい。It is even better to use a material doped with a protonic acid such as 1-6so, or an alkali metal such as Ll, Na, or K, since the conductivity is further improved by light irradiation.
ドープ量としては普通10−I〜0.5モル%(単位モ
ノマー当シのモル%)供される。The doping amount is usually 10-1 to 0.5 mol % (mol % based on unit monomer).
また、上記高分子樹脂は、予じめ、Ag1Cu等の金属
微粒子が分散させられたものであるとなおよい。この場
合、上記高分子樹脂が絶縁性を失わない範囲で分散させ
ておくことは云うまでもない。Further, it is even better if the polymer resin is one in which fine metal particles such as Ag1Cu are dispersed in advance. In this case, it goes without saying that the polymer resin should be dispersed to the extent that it does not lose its insulation properties.
以下、実施例を用いて詳述する。Hereinafter, it will be explained in detail using examples.
第2図は本発明の一実施例としての平坦化配線を用いた
電気素子の概略斜視図である。FIG. 2 is a schematic perspective view of an electric element using planarized wiring as an embodiment of the present invention.
図において、セラミック基板21上に、−辺が1の、膜
厚50μmのポリイミド・シート22が設けられている
。CO,ガスレーザ光をスポット径40pmに絞って上
記シート22を所定のパターンに走査させると、照射さ
れた部分24は導電領域になっている。この導電領域2
4の導電率は10”ρ−1o11°1である。絶縁領域
23に仕切られておシ、上記導電領域24は抵抗体とし
ても使用できた・上記抵抗体の端部に9−ド線25が接
続されて電気素子が構成される。In the figure, a polyimide sheet 22 with a negative side of 1 and a film thickness of 50 μm is provided on a ceramic substrate 21. When the sheet 22 is scanned in a predetermined pattern by narrowing the CO or gas laser beam to a spot diameter of 40 pm, the irradiated portion 24 becomes a conductive area. This conductive area 2
The electrical conductivity of 4 is 10"ρ-1o11°1. The conductive region 24 can also be used as a resistor by being partitioned into an insulating region 23. A 9-wire 25 is connected to the end of the resistor. are connected to form an electric element.
この様に、本発明では、第3図の部分工程図に示す様に
絶縁性高分子で基板もしくは、基板の一部を形成31し
、レーザー光を配線形成したい領域に照射32する。レ
ーザー光の照射された領域のみが導電性となシ、少ない
工程数で配線形成ができる。As described above, in the present invention, as shown in the partial process diagram of FIG. 3, a substrate or a part of the substrate is formed 31 using an insulating polymer, and a region where wiring is to be formed is irradiated 32 with laser light. Only the area irradiated with laser light becomes conductive, allowing wiring to be formed with fewer steps.
第4図は本発明の他の実施例としての平坦化配線を用い
た電気素子の概略断面図である0図において、81結晶
41に所定の導電型の不純物拡散領域42が形成されで
いる。上記結晶41および一部拡散領域42上に5iQ
1膜43が形成され1該膜43上および上記拡散領域4
2上にA/、薄膜44が形成されている。上記At薄膜
44および上記8i0.膜43上に膜厚1〜50μmの
ポリイミド薄膜451を形成する。この薄膜は塗布法、
浸漬法など公知の形成法でよい。この薄膜の固化後、所
定のパターンのマスク(図示せず)を便用してレーザー
光照射を行ない上記At薄膜44上の一部のポリイミド
薄膜45を導体化する。FIG. 4 is a schematic cross-sectional view of an electric element using flattened wiring as another embodiment of the present invention. In FIG. 5iQ on the crystal 41 and a part of the diffusion region 42.
A film 43 is formed on the film 43 and the diffusion region 4.
A thin film 44 is formed on A/2. The above At thin film 44 and the above 8i0. A polyimide thin film 451 having a thickness of 1 to 50 μm is formed on the film 43. This thin film is made by coating method,
A known forming method such as a dipping method may be used. After this thin film is solidified, a portion of the polyimide thin film 45 on the At thin film 44 is made conductive by irradiating laser light using a mask (not shown) with a predetermined pattern.
樹脂層451の一部を光照射によシ導電化するので、絶
縁部分451の高さと導体層45の高さとは同一水準に
あり、平坦面が形成されている。図では、下地のAt層
44と導体層45が電気的に接続されているが、クロス
オーバ配線などの配線層(図示せず)とする場合は樹脂
層451内に独立して設けられる。Since a portion of the resin layer 451 is made conductive by light irradiation, the height of the insulating portion 451 and the height of the conductor layer 45 are at the same level, and a flat surface is formed. In the figure, the underlying At layer 44 and the conductor layer 45 are electrically connected, but when used as a wiring layer (not shown) such as a crossover wiring, they are provided independently in the resin layer 451.
次いで、ポリイミド液の塗布、固化、光照射が前述と同
じ方法で順次繰シ返えされて、多層配線構造体を有した
集積回路を擁した電気素子が形成される。レーザー光照
射は、また、1000人程度O7ルミニウムで配線形成
領域以外を覆い、全面にレーザー光照射しても配線形成
はできる。The application, solidification, and light irradiation of the polyimide solution are then repeated in sequence in the same manner as described above to form an electrical device having an integrated circuit with a multilayer wiring structure. The wiring can also be formed by covering the area other than the wiring formation area with about 1000 O7 aluminum and irradiating the entire surface with laser light.
本発明は、更に他の改良が可能である。上記ポリイミド
薄膜]51にAIIP、等をドープさせると導電率が3
割から1桁以上大きくなって改善された。このドープは
、例えば、圧力1〇−畠〜l’porrで常温のAIF
、ガス中に1時間〜数日間放置することによシ得られる
。これは、上記ポリイミドの代)に、ポリアクリロニト
リル、ボリアオドイミド、フェノール樹脂、ポリフェニ
レン、ポリフェニレンスルフィド、ポリアセチレンヲ用
いてモ同様の効果が得られた。また、上記ドープ剤とし
て、■!、BrI、Ct*7!:トノハロゲン分子、H
!So。The invention is capable of further improvements. When the above polyimide thin film] 51 is doped with AIIP, etc., the conductivity increases to 3.
This was an improvement of more than an order of magnitude compared to the previous year. This dope, for example, is applied to AIF at room temperature at a pressure of 10-10 to 1'porr.
, by leaving it in a gas for 1 hour to several days. Similar effects were obtained by using polyacrylonitrile, boriaodoimide, phenol resin, polyphenylene, polyphenylene sulfide, and polyacetylene in place of the above-mentioned polyimide. In addition, ■! as the above doping agent! ,BrI,Ct*7! : Tonohalogen molecule, H
! So.
などのブートン酸、AIF、をはじめとしたルイス酸e
LltNa、xなどのアルカリ金属も差違なく同様に適
用でき、同様の効を奏した・
本発明は、更に又、次の改良が可能である。例、tば〜
ポリイミド・シートを形成する際に、シートが絶縁性を
失わない範囲で微量の金属(AgeC”*他)微粒子を
分散させておくと良い。この場合には1配線部分の導電
率がさらに向上する。Lewis acids such as boutonic acid, AIF, etc.
Alkali metals such as LltNa and x can be similarly applied without any difference, and the same effects were obtained.The present invention can also be improved as follows. Example, tba~
When forming a polyimide sheet, it is best to disperse a small amount of metal (AgeC''* etc.) fine particles to the extent that the sheet does not lose its insulating properties.In this case, the conductivity of one wiring section will further improve. .
上述の実施例では、レーザー光にco禦ガスレーザーを
用いたが、他のガスレーザ、固体レーザ。In the above-mentioned embodiment, a cobalt gas laser was used as the laser beam, but other gas lasers and solid-state lasers may be used.
半導体レーザを使用しても全く同様に適用できた。Even if a semiconductor laser was used, it could be applied in exactly the same way.
これら屯レーザー光の波長および高分子の吸収係数に基
づいて適宜選べばよい。It may be selected as appropriate based on the wavelength of these laser beams and the absorption coefficient of the polymer.
以上祥述した様に、本発明は、絶縁性の高分子樹脂膜の
光照射部分を導電性に変換させて平坦化配線を提供し得
る点、極めて製法が容易で、且つ電気的特性をも良好で
あって、工業的利益大なるものである。As described above, the present invention is capable of providing flattened wiring by converting the light-irradiated portion of an insulating polymer resin film into conductive, and is extremely easy to manufacture and has excellent electrical characteristics. It is of good quality and has great industrial benefits.
第1図は従来の製法の概略工程図、第2図は本発明の一
実施例としての平坦化配線を用いた電気素子の概略斜視
図、第3図は第2図に用いた部分工程図、第4図は本発
明の他の実施例としての平坦化配線を用いた電気素子の
概略断面図である。
21・・・セラミック基板、22・・・ポリイミド薄膜
、23・・・ポリイミド薄膜(絶縁部分)、24・・・
ポリ′¥J 1 困
fJ 2 図
’l!i3 図
% 4 図Fig. 1 is a schematic process diagram of a conventional manufacturing method, Fig. 2 is a schematic perspective view of an electric element using flattened wiring as an embodiment of the present invention, and Fig. 3 is a partial process diagram used in Fig. 2. , FIG. 4 is a schematic cross-sectional view of an electric element using planarized wiring as another embodiment of the present invention. 21... Ceramic substrate, 22... Polyimide thin film, 23... Polyimide thin film (insulating part), 24...
Poly'¥J 1 troublefJ 2 Figure'l! i3 Figure% 4 Figure
Claims (1)
に6る導電層を有した平坦化配線において、上記導電層
は絶縁性高分子が光照射されて導体化されたところの高
分子樹脂膜であることを特徴とする平坦化配線。 2、特許請求の範囲第1項において、上記高分子樹脂は
、ポリイミド、ポリアクリロニトリル。 ボリア建トイ建ド、フェノール樹脂、ポリフェニレン、
ポリフェニレンスルフィト、ポリアセチレンの中から少
く共1者を用いてなることを特徴とする平坦化配線。 λ 特許請求の範囲第1項において、上記高分子樹脂膜
は、ハルフッ分子、ルイス酸、プロトン酸、および、ア
ルカリ金属の中から少く共1者がドープされてなること
を特徴とする平坦化配線。 4 特許請求の範囲第1項において、上記高分子樹脂膜
は、金属微粒子を分散せしめてなることを特徴とする平
坦化配線。[Claims] 1. In a flattened wiring formed on a substrate and having a flat surface and conductive layers arranged at approximately the same height, the conductive layer is made of an insulating polymer that is irradiated with light to become a conductor. 1. A flattened wiring characterized by being a polymer resin film. 2. In claim 1, the polymer resin is polyimide or polyacrylonitrile. Boria construction toy construction, phenolic resin, polyphenylene,
A flattened wiring characterized by using at least one of polyphenylene sulfite and polyacetylene. λ In claim 1, the planarized wiring is characterized in that the polymer resin film is doped with at least one of a half-fluoride molecule, a Lewis acid, a protonic acid, and an alkali metal. . 4. The planarized wiring according to claim 1, wherein the polymer resin film is formed by dispersing fine metal particles.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP10934081A JPS5812392A (en) | 1981-07-15 | 1981-07-15 | Flattened wire |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP10934081A JPS5812392A (en) | 1981-07-15 | 1981-07-15 | Flattened wire |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5812392A true JPS5812392A (en) | 1983-01-24 |
Family
ID=14507740
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP10934081A Pending JPS5812392A (en) | 1981-07-15 | 1981-07-15 | Flattened wire |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5812392A (en) |
Cited By (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS59204941A (en) * | 1983-05-04 | 1984-11-20 | 帝人株式会社 | High density water repellent cloth |
JPS6189234A (en) * | 1984-10-02 | 1986-05-07 | イー・アイ・デユポン・ド・ネモアース・アンド・コンパニー | Sintering of metal middle layer in organic polymer film |
US4694138A (en) * | 1984-02-10 | 1987-09-15 | Kabushiki Kaisha Toshiba | Method of forming conductor path |
US4969979A (en) * | 1989-05-08 | 1990-11-13 | International Business Machines Corporation | Direct electroplating of through holes |
JPH07153758A (en) * | 1993-12-01 | 1995-06-16 | Nec Corp | Semiconductor device and manufacturing method |
US6444400B1 (en) * | 1999-08-23 | 2002-09-03 | Agfa-Gevaert | Method of making an electroconductive pattern on a support |
US7504150B2 (en) | 2005-06-15 | 2009-03-17 | E.I. Du Pont De Nemours & Company | Polymer-based capacitor composites capable of being light-activated and receiving direct metalization, and methods and compositions related thereto |
US7531204B2 (en) | 2005-06-15 | 2009-05-12 | E. I. Du Pont De Nemours And Company | Compositions useful in electronic circuitry type applications, patternable using amplified light, and methods and compositions relating thereto |
-
1981
- 1981-07-15 JP JP10934081A patent/JPS5812392A/en active Pending
Cited By (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS59204941A (en) * | 1983-05-04 | 1984-11-20 | 帝人株式会社 | High density water repellent cloth |
JPS6336380B2 (en) * | 1983-05-04 | 1988-07-20 | Teijin Ltd | |
US4694138A (en) * | 1984-02-10 | 1987-09-15 | Kabushiki Kaisha Toshiba | Method of forming conductor path |
JPS6189234A (en) * | 1984-10-02 | 1986-05-07 | イー・アイ・デユポン・ド・ネモアース・アンド・コンパニー | Sintering of metal middle layer in organic polymer film |
US4969979A (en) * | 1989-05-08 | 1990-11-13 | International Business Machines Corporation | Direct electroplating of through holes |
JPH07153758A (en) * | 1993-12-01 | 1995-06-16 | Nec Corp | Semiconductor device and manufacturing method |
US6444400B1 (en) * | 1999-08-23 | 2002-09-03 | Agfa-Gevaert | Method of making an electroconductive pattern on a support |
US7504150B2 (en) | 2005-06-15 | 2009-03-17 | E.I. Du Pont De Nemours & Company | Polymer-based capacitor composites capable of being light-activated and receiving direct metalization, and methods and compositions related thereto |
US7531204B2 (en) | 2005-06-15 | 2009-05-12 | E. I. Du Pont De Nemours And Company | Compositions useful in electronic circuitry type applications, patternable using amplified light, and methods and compositions relating thereto |
US7547849B2 (en) | 2005-06-15 | 2009-06-16 | E.I. Du Pont De Nemours And Company | Compositions useful in electronic circuitry type applications, patternable using amplified light, and methods and compositions relating thereto |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP3154713B2 (en) | Anisotropic conductive film and method for manufacturing the same | |
US3846166A (en) | Method of producing multilayer wiring structure of integrated circuit | |
EP0159443B1 (en) | Method of forming conductor path | |
US3890636A (en) | Multilayer wiring structure of integrated circuit and method of producing the same | |
US2693023A (en) | Electrical resistor and a method of making the same | |
US4685014A (en) | Production method of thin film magnetic head | |
JPS5812392A (en) | Flattened wire | |
EP0105639A2 (en) | Production of resistor from insulating material by local heating | |
JPS58108763A (en) | Method of trimming laser die plate for circuit element | |
US4692387A (en) | Sintering of metal interlayers within organic polymeric films | |
US4719443A (en) | Low capacitance power resistor using beryllia dielectric heat sink layer and low toxicity method for its manufacture | |
US20060096780A1 (en) | Thin film circuit integrating thick film resistors thereon | |
JPS61244094A (en) | Manufacture of multilayer wiring board | |
JPH07335440A (en) | Electronic part having polyimide substrate and manufacture thereof | |
JPS59107592A (en) | Board for printed circuit | |
JPS60244093A (en) | Method of producing circuit board | |
JPS62229903A (en) | Formation of resistance element | |
JPH04217386A (en) | Manufacture of circuit | |
JPS63287042A (en) | Substrate for circuit | |
KR810000190B1 (en) | Printed circuit and method of making | |
JPS5955090A (en) | Method of producing flexible circuit board with resistor | |
JPS63141358A (en) | Method for adjusting value of resistance element | |
JP4108421B2 (en) | Plastic circuit element and manufacturing method thereof | |
JPS59169107A (en) | Method of producing resistor | |
JPS6052095A (en) | Multilayer circuit board and method of producing same |