JPS58123250A - Data reception switching method - Google Patents

Abstract

PURPOSE:To prevent the occurrence of an error by associating the switching point of a receiver with the switching point of data. CONSTITUTION:Data signals of the same kind inputted to receivers 1 and 2 do not have equal signal levels all the time, so received signals with different levels are outputted. Those outputs are demodulated by the 1st demodulator 5 and the 2nd demodulator 5a to output digital data to the 1st clock regenerating circuit 6, the 2nd clock regenerating circuit 6a, and a switch circuit 10. The 1st and the 2nd clock regenerating circuits 6 and 6a output the 1st and the 2nd clocks for deciding on the sampling point of data so that the error rates of the input ditital data are optimum. Those 1st and 2nd clocks are inputted to a clock switch 9. A deciding circuit 7 samples the data by sampling pulses from the switch circuit 9 or 10 so that the error rate is optimum.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a data reception switching method that can eliminate malfunctions during data reception switching.

FIG. 1 is a block diagram showing a conventional data reception switching method. In the figure, (1) and ■ are reception signals that output received signals (the signal strengths (levels) of which do not necessarily match) obtained by separately receiving the same data signal with diversity using, for example, two antennas (not shown). The receiver (2) compares the OV level of the received signal output from the receiver (1) with the level of the received signal output from the receiver (2), and determines, for example, that the level of the received signal from the receiver (1) is higher. When the received signal level of the receiver (2) is higher, it outputs a high-level instruction signal, and when the received signal level of the receiver (2) is higher, it outputs a lower-level instruction signal. A switch circuit (Ω) which switches to output the received signal of the receiver (1) when the level is high and output the received signal of the receiver (2) when the input instruction signal is low level demodulates the received signal. (6) is a first demodulator that outputs digital data.
), the first clock re-halving circuit (ff) outputs the first clock that determines the data sampling point so that the error rate of the digital data output from the clock is optimized. This is a judgment circuit that judges data at the change point in (lower C).

Next, the operation of the data reception switching circuit having the above configuration will be briefly explained. First, receiver (1) and receiver (
Since the same data signals input to 2) do not necessarily match in signal strength (level), received signals of different levels are output. therefore,
The reception level comparator (3) compares the levels of these two reception signals, and when the level of the reception signal of the receiver (1) is higher than the level of the reception signal of the receiver (2), it indicates a high level. The signal is output to the switch circuit (Xun). Therefore, upon input of this high-level instruction signal, the switch circuit (4) is switched to select and output the signal received by the receiver (1). The received signal of the receiver (1) is passed through this switch circuit (4) to the first demodulator (
5), demodulated into a digital signal, and sent to the judgment circuit (
1) Enter. This judgment circuit (7) determines the data sampling point so that the data error rate is optimized. The data is sampled at the change point and data is received.

However, in the conventional data reception switching method, there is no correlation between data change points and reception level fluctuations, so if the receiver switches near the data sampling point, there are drawbacks such as malfunction due to switch noise. Ta.

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a data reception switching method that can eliminate errors by associating the receiver switching time with the data switching time.

In order to achieve such an object, the present invention outputs a sampling pulse at the rising edge (or falling edge) of the clock obtained from each received signal, and outputs a sampling pulse at the falling edge (or rising edge 9) of the clock obtained from each received signal. This system is designed to output a switching signal for selectively switching to a received signal with a high signal level or demodulated digital data, and will be described in detail below using an embodiment.

FIG. 2 is a circuit diagram showing an embodiment of the data reception switching method according to the present invention. In the same figure, (5a-Kin receiver (
a second demodulator (6a) that demodulates the received signal output from 2) and outputs the digital data shown in FIG. 3(a);
is a second clock recovery circuit which determines the data sampling point so that the error rate of the digital data outputted from the second demodulator (5a) is optimized, and outputs the second clock shown in FIG. 3(e). , (8) inputs the instruction signal of the reception level comparator (2) (the instruction signal shown in FIG. 3 shows an instruction signal that has changed to a high level) to its input terminal (8a), and the input terminal (
8b) is inputted with a first switching clock shown in FIG. 3(g) or a second switching clock shown in FIG. ), the switching signal latch circuit (9) outputs the switching signal shown in FIG. 3 to its input terminal (9a), and the first clock shown in FIG. The second clock shown in e) is input and output from the output terminal (9C) at the falling edge change point of the first clock. The second switching clock shown in FIG. 3 (Q) outputs, the switching signal is input to the input terminal (9d), and the output terminal (9e)
From then on, the first sampling pulse is output at the rising edge of the first clock (see Figure 3 (C)) or the second sampling pulse is output at the rising edge of the second clock (see Figure 3 (F)). ) output clock switch circuit, (
1G) has a first demodulator (5) at its input terminal (10a).
The digital data to be output from the input terminal (1
0b) is input with digital data output from the second demodulator (5a), input terminal (10c) is input with a switching signal, and output terminal (10a) is input with digital data output from the first demodulator (5) or This is a switch circuit that outputs one side of the digital data of the second demodulator (5a).

In addition, to explain the operation of the switching signal latch circuit (8), when the second switching clock is input to the input terminal (8b) while a high level instruction signal is input to the input terminal (8a). , the 6 force state is reversed and the output terminal (8
c) outputs a high-level switching signal, and outputs a high-level switching signal from the input terminal (8a
), when the first switching clock is input to the input terminal (8b), the output state is inverted and a low level switching signal is output from the output terminal (8c). Also, to explain the operation of the clock switch circuit (9), when a high-level switching signal is input to the input terminal (9d), the output state is inverted, and the output terminal (9d) is inverted.
The first switching clock is output from c), and the output terminal (9e)
The first sampling pulse is output from the output terminal (9C), and when a low-level switching signal is input to the input terminal (9d), the output state is reversed, the second switching clock is output from the output terminal (9C), and the output terminal (9e) outputs the first sampling pulse. When a high-level switching signal is input, the output state is reversed, and the digital data of the received signal of the receiver (1) is output from the output terminal (10a), and a low-level switching signal is input to the input terminal (10c). Then, the output state is reversed, and the digital data of the received signal of the receiver Q) is output from the output terminal (10d).

Next, we will discuss the operation of the data reception switching method with the above configuration.
This will be explained with reference to FIG. 3(?-) to FIG. 3(1).

First, since data signals of the same type inputted to receiver (1) and receiver (2) do not necessarily match in signal strength (level), they output received signals of different levels. The received signals output from the receiver (1) and the receiver (2) are respectively sent to the first demodulator (
5) and the second demodulator (5a). The first demodulator 0) and the second demodulator (5a) each demodulate the input received signal and convert the digital data into the first clock recovery circuit (6), the second clock recovery circuit (6a), and the second demodulator (5a), respectively. Output to the switch circuit (10). The first clock regeneration circuit (6) and the second clock regeneration circuit (6a) respectively use the first clock and second clock regeneration circuits to determine the data sampling point so that the error rate of the input digital data is optimized. The second clock is input to the clock switch circuit (9).

Here, to simplify the explanation, it is assumed that the level of the received signal of the receiver (2) is higher than the level of the received signal of the receiver (1). In this state, the instruction signal output from the reception level comparator (3) is at a low level. Also, the output terminal (9c) of the clock switch circuit 0) is the third
The second switching clock shown in Figure (b) is output. Then, a low level switching signal is output from the output terminal (8c) of the switching signal latch circuit (8). Therefore, from the output terminal (9e) of the clock switch circuit (9) to
) is output, and the digital data of the received signal received by the receiver (2) is output from the output terminal (11a) of the switch circuit (10). It is assumed that the determination circuit (7) is in a state in which digital data is sampled by the second sampling pulse and data is being received so that the data error rate is optimized. Next, in such a receiving state, the operation when the level of the received signal of the receiver (1) becomes higher than the level of the received signal of the receiver (2) is shown in FIGS. 3(a) to 3(a). This will be explained with reference to FIG. 3 (1). In such a state, the instruction signal output from the reception level comparator (3) is at the quotient level as shown in FIG. 3(b). Therefore, the second clock signal shown in FIG. 3 (b) output from the output terminal (9c) of the clock switch (3)
The switching clock is connected to the input terminal of the switching signal latch circuit (8) (
8b), this switching signal latch circuit (8)
is switched), and outputs a flat-level switching signal shown in FIG. 3) from its output terminal (8c) to the clock switch circuit Φ) and the switch circuit (10).

Therefore, the clock switch circuit (9) is switched by a high-level switching signal input to its input terminal (9d), and outputs the first sampling pulse shown in the third section from its output terminal (9c). Further, the switch circuit (10) is switched by a high-level switching signal inputted to its input terminal (10c) 9, and its output terminal (10a)
711- outputs digital data of the received signal received by the receiver (1). Therefore, the determination circuit (1) can receive data by being sampled by the first sampling pulse that optimizes the data error rate.

In the above embodiment, the data is converted to digital data and then inputted to the switch circuit for switching, but it is of course possible to switch by synchronizing with the reception clock using an analog signal before converting to digital data. Furthermore, in the above embodiment, the sampling pulse is generated at the rising edge of the first clock or the second clock, and the first switching clock or the second switching clock is generated at the falling edge of the clock, but the sampling pulse is generated at the falling edge of the clock. Of course, the first switching clock or the second switching clock may be generated at the rising edge of the switching clock.

As explained above in detail, according to the data reception switching method according to the present invention, the switching point of the receiver is switched in synchronization with the received data, so there is an effect that data reception switching can be performed without errors. .

[Brief explanation of drawings]

Figure 1 is a circuit diagram showing a conventional data reception switching method;
The figure is a circuit diagram showing an embodiment of the deprivation data reception switching method according to the present invention, and FIGS. 3(a) to 3(1) are time charts showing the operation of each part of the second function. (1) and (2)...receiver, (3)...reception level comparator, (4)...switch circuit, (5)
...First demodulator, (5a) ...Second demodulator, (
6)...First clock regeneration circuit, (6a)...
Second clock regeneration circuit, (T)...determination circuit, (8
)...Switching signal latch circuit, (S)...Clock switch circuit, (10)...Switch circuit. In addition, in the figures, the same reference numerals indicate the same or corresponding parts. Agent Shin Kuzuno (1 other person) ゛( Figure 1 Figure 2, b Figure 3 4 (i) -11-]-

Claims (1)

[Claims] The same data is received separately by two receivers, and the signal level
In a data reception switching circuit that selectively switches to a high received signal or demodulated digital data, and receives the data by sampling the digital data with a sampling pulse, the rising edge of the clock obtained from each received signal At the falling edge (or rising edge) of the clock, a sampling pulse is output, and at the falling edge (or rising edge) of the clock, a switching signal is output that selectively switches to the received signal with a higher signal level or its demodulated digital data. A data reception switching method characterized in that: