JPS5812035A - Detection circuit for clock signal malfunction - Google Patents

Abstract

PURPOSE:To detect malfunction of clocks with a comparatively simple circuit, by making error detection when a point of time of clock signal counted for a prescribed number has come out of a scheduled period. CONSTITUTION:The 2nd counter 2 counting with another test clock signal CP2 independently from a clock signal CP1 is provided, and when the clock signal CP1 is counted for a prescribed number within a scheduled period determined with the 2nd counter 2, it is regarded as normal, and if a point of time counted for the clock signal CP1 for a prescribed number has come out of a scheduled period, error detection is made. Thus, with the test clock signal CP2, a failure in the clock signal CP1 can be detected with a simple logical circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention is applicable to data processing within a data processing device or to data processing! 1It
The present invention relates to a clock signal malfunction detection circuit for detecting a malfunction of a clock signal in which a clock signal is detected.

Each part in the data processing device is operated by a clock signal, and if there is a drop in the clock signal, or if the lock signal is excessive due to noise etc., the operation of each part will be incorrect, and the data processing result will be incorrect. . If the number is 1, there is a risk that the system will go down. However, it is relatively difficult to detect malfunctions in the clock signal and address bus.

Rounding is not easy, such as when a malfunction occurs in a data bus, etc.
Generally, a simple method for detecting malfunctions of clock signals is used.If necessary for %/%fk-0q#, malfunction detection is performed by duplicating the clock system circuits and constantly comparing their outputs. Teru. However, even in this case, the Kutsuk source is the same.If the 9th input clock itself is incorrect, it will not be effective, and the use of 9.2 Kutsuk sources will cause a difference no matter how precise the tarotsuta is used. This is because Tsukusome is limited to one. Another known method is to use a monostable multivibrator to detect if there is no clock for more than -Hiroshi time, but in this case, there are problems with the accuracy of the monostable multivibrator. Ashi,
On the other hand, there is a drawback that the number of clocks increases due to noise, etc., making it impossible to detect 9 cases.

An object of the present invention is to provide a clock signal malfunction detection circuit capable of detecting clock malfunction with a relatively simple 1 kWi circuit.

The detection circuit of the present invention includes a first time measuring circuit comprising a counter or register, etc., which outputs a clock signal according to a certain number of clock signals, and a test clock generating circuit, which generates a test signal independent of the clock signal. And, it operates according to the test tarok signal, and there are two types of diameter reduction at the scheduled time! a second time hand side circuit that outputs a sampling signal; and a synchronization circuit that resets the first time measurement circuit in synchronization with the start of operation of the second time measurement circuit, Output of time measurement - The membrane chamber is configured to output two types of signals from the hour hand I1wA before and after time 0, and the above! It is characterized in that the one-hour meter-circuit O output signal is output outside the scheduled time and an error signal is output at nine o'clock.

Next, the present invention will be explained in detail with reference to the drawings.

Figure 1 is a block diagram showing one embodiment of the present invention.

That is, in this embodiment, the counter l is the first hour hand III.
Il path, counter 2 is ll12 hour hand IIIl
It is a road. The counter 111 counts the clock signal CP, and the counter 2 counts the test clock signal CP. The test clock signal CP*tjxll is an arbitrary period test clock signal generated by the test clock signal generation circuit independently of the clock signal CP. Then, the counter 1tlj outputs an output signal 11 at the negative value V, and outputs the output signals 22 and 23 at the constant count values N and N-α of the three colors, and the counter 2O first stage 1. The signal = 1 is input to the D terminal exclusively for the first stage circuit, and is output to the Q terminal by the tarok signal CP input to the CP terminal. The counter 1 is reset by the q output 311 of the synchronization circuit 3, and the counter 1 starts counting with the clock signal 'cP, 0, and when the count reaches M, the output signal 110 becomes @1m.

The counter 2 counts the test signal CP and sets the logic of the output signal 22 to @11 with the count value N-α.
The output signal 23e logic is set to 11''' at the count value N, and the am's operation is performed. Before inputting the output signal 11 of counter 1 to the good signal and the output signal 23 of counter 2,
and are connected to the same power of the error machine output 4 through an AND circuit 6. An error signal 41 is output by the error detection circuit 4ti, the AND circuit 5 or Fi- whose output logic is 11#, and the self-test clock signal CP. The above-mentioned counter 1 outputs the clear open bale tally signal CP at a frequency V times the period me, and the counter 1 outputs the period me of the clear open bale tally signal CP.
The period of , is output in N-4 times and N times as long as the period of , .

And (N el ) tg < 11 + M Tl <
KM, N, and N-α are set so that N rg. Two kinds of output signals 111O are output before and after the scheduled time of output signals 22 and 23Fi? This is a printer signal. It should be noted that the small swA motion detection accuracy of the solid sensor that satisfies the above equation is good.

Next, the operation of this embodiment will be explained with reference to FIG. 1 and the first intention. FIG. 2 is a time chart showing the logical states of the main parts in FIG. Counter 1 has
As shown in FIG.
is input, and the period τ! as shown in (41) in the same figure is input to the counter 2. A test clock signal CP is input. The counter 2 sets the logic of the first stage signal 21 to @1'' during the first clock period of the test clock signal CP (see FIG. 2 ()).

The first stage signal 21 is inputted to the D terminal of the synchronous circuit 3, and inputted to the FiCP terminal of the synchronous circuit 3, or the logic m of the output signal 31 is set to @l# at the time of rising of the ivy signal cp-. (See Figure 2), synchronous circuit 3Fi, for example DIl
Flip 7■ Can be configured by tabs. The counter 1 is reset by the output signal 31 of the synchronous circuit 3, the counter IFi counts the subsequent clock signal CP, and when the count value is MK*, the output signal 11 is output. ), the output signal 11tj
, the elapsed time after reset is y, and the logic becomes @11. On the other hand, when the count value of the test clock signal CP snow reaches N-α, the counter outputs the output signal 22 (for one time clock period), and at the count value N, outputs the output signal 23 (for one time clock period). do. That is, the time (N-α) from the first pulse rising point of the test clock signal CP
τSignal with snow! 2, the signal 23 is output at time N y (see Figure 2 (f) and -), (N - α) τ, , N
r, and My.

Since the relationship is given by the above-mentioned 2, the time point at which the output signal 11 of the counter 1 rises should be located between the output signals 22 and 230 of the counter 2. Therefore,
The outputs of the AND circuits 5 and 6 are both @O'', and the error detection circuit 4tj does not output the error 4!41. However, if the clock signal CP increases abnormally due to some reason, , because the rise time of the output signal 11 of the counter 1 is earlier than K, the output of the AND circuit 5 overlaps with the period of the logic 111 of the output signal 22 of the counter 2, and the error detection circuit 4F1 outputs the error signal 41 ( If the st* clock signal CP is missing for some reason, the rising point of the output signal 110 of the counter 1 will be delayed, so the output signal of the AND circuit 6 will become @1#. In other words, if counter 1 is reset and the lock signal is normal, the M of the lock signal is detected.
Output signal 22 from counter 2 before and after the second rising time
and 23, and the output signal of counter 1 is 1! If the time point at which the signal 11 rises is an intermediate point in time between the above two signals, it is considered normal, and if the signal 11 rises during the output period of either of the above two signals, an error signal is output. Since the tarot signal CP1 and the test clock signal CP are mutually independent, the time points at which the power meeting 1 and the counter 20 start counting are shifted within the range of 1 week period of the test test signal CP. is normal, counter 1 by lock signal
The rising edge of the output signal 11 of , the signals 22 and 230
If you look at it, the test clock signal CP should be set so that it is located in the middle.
It can also be considered that an error signal is output when the number of pulses of the clock signal CP, which occurs during a certain period set by , is not the expected number (M).

FIG. 3 shows another embodiment of the present invention. In this case, a shift register 7 and a shift register 8 are used to configure the first and second time measurement circuits. The output 21' of the first stage is input to the shift register 7, and the shift register 7 receives the clock signal CP.
, performs a sequential shift operation. Since the first stage (φG) of the shift register 7 receives the output 21' and outputs the output 31' at the rising edge of the four-way signal CP, the first stage (◆0) of the shift register 7 constitutes a synchronous circuit. There is. The output 31' sets the 7V output 9, and at the same time, it is sequentially shifted by the subsequent clock signal. Then, the output from the φ violet stage of the shift register T resets the aperture block 9. The output signal 11' of the tripper knob 110Q terminal is expressed as ``l'' at the time of reset. At that time, the output signal of the Q terminal becomes ``ist@o'', so the AND circuit !I, 6o input signal is , as in the case of 9 shown in FIG.
is shifted by the test clock signal CP, and connects the (N-α)th output 22' and the N#rF4 output 23' to the other input of the AND path s:sP and 6, respectively. do. Therefore, the output of one of the AND circuits ls, . . . As in the case of the example, if the o-th start-up time of the o-th cover falls outside the scheduled range, the error will be displayed as "1" and an error will be detected by the error detection circuit 4.

As described above, in the present invention, the time is measured using the test signal I, which is independent of the four-way test No. 1.
l! A time measuring circuit is provided, and when the clock signal is counted a certain number of times within the preliminary period determined by the second hour hand m circuit, the clock signal is determined to be normal, and when the clock signal is counted a certain number of times and the clock signal runs during the above scheduled period. Since the circuit is configured to detect an error when the clock signal deviates from the clock signal, it is possible to detect an abnormal increase or omission of the clock signal with a simple logic circuit using a test clock independent of the clock signal.

[Brief explanation of the drawing]

FIG. 1 is a block diagram including a logic circuit showing one embodiment of the present invention, FIG. 2 is a time chart showing signals of each part of the above embodiment, and FIG. 3 is a block diagram showing another embodiment of the present invention. FIG. In the figure, 1.2-open door, 3-synchronous circuit, 4-error detection circuit, 5.6-AND circuit, 7°8...shift register, 9-flip flop. Figure 3

Claims (1)

[Claims] A time measurement circuit consisting of a counter that outputs a constant number of clock signals, a test clock generation circuit that generates a test clock signal independent of the above-mentioned logic signal, and a test clock. a second time measuring circuit that operates according to a clock signal and outputs a sampler signal of 2 seconds before and after the scheduled time; and resetting the first hour hand #41il path in synchronization with the start of operation of the first time measuring circuit. and a synchronization circuit, and is set to output a sump 9y da code of class 211 from the second time measuring circuit 11K before the output time of the first time measuring circuit due to the normal clock signal. A clock signal malfunction detection circuit, characterized in that it outputs an error signal when the output signal of the first time hand control circuit is output outside the scheduled time.