JPS58119071A - Information processor - Google Patents

Abstract

PURPOSE:To control both a CPU and an auxiliary processor through one control line, by using only one data transfer synchronizing signal line as the control line between the CPU and auxiliary processor. CONSTITUTION:The CPU1 is so devised that an auxiliary processor synchronizing line (APS)11 is provided as a substitute for an internal state display line output. The auxiliary processor (AP)2 connects with the APS11 as a substitute for a state display line 4 and connects with neither of an address bus 5 nor an address synchronizing line 6. When the CPU1 is to receive data from another device, data synchronism 8 shows that a value on the data bus is set up. When the CPU1 is to send data to another device, the data bus synchronism 8 shows that the device to receive the data has stored the data. In either case, that is reported to a microprogram.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a central processing unit and an auxiliary processing unit of a microcomputer system.

In conventional microcomputer systems, when a central processing unit controls an auxiliary processing unit to improve its performance or functionality, the internal state of the central processing unit is communicated to the auxiliary processing unit through a dedicated signal line. FIG. 1 shows a schematic connection of a conventional central processing unit (hereinafter abbreviated as CPU) 1, an auxiliary processing unit (hereinafter abbreviated as AP) 2, and a main storage device 3. These are address buses 5. Address synchronization 6. They are interconnected by a data bus 7 and a data synchronizer 8. In this example, we are considering 16 bits of address and 16 bits of data, so the address bus 5. Data bus 7 shows 16 wire bundles. Also CPUI
and AP2 are coupled by a status indicator line 4 that indicates the internal status of the CPU (for example, 16 independent next statuses). This is a bundle of lines with a sufficient number (four lines in this example) to display the internal state of the CPU. AP2 sequentially detects the internal state of the CPU and checks the values on the data bus 7.

When the auxiliary processing unit learns that the value on the data bus 7 is an instruction code, it determines whether or not it is the instruction that it should process, and when it learns that it is its own instruction, it specifies it with the instruction code. A new processing routine was being started. In this way, CPU1 informs AP2 of its internal status through a dedicated signal line (
This resulted in an increase in the number of bins in the package.

Furthermore, when AP2 obtains data (operands) necessary for an operation, the CPU reads only the first operand from the main memory 3, and AP2 reads the second and subsequent operands. 32 pieces) were required. The AP2 reads the address of the first operand outputted by the CPU via this bin, and reads the second and subsequent operands based on this address.

In this way, conventionally the CPU required many bins to control the APZ.

An object of the present invention is to provide an information processing apparatus that controls a central processing unit and an auxiliary processing unit using one control line.

The present invention provides control at-
There is only one data transfer synchronization signal line, and the data required by the auxiliary processing unit (instruction codes, operands, etc.) is read when the central processing unit starts reading from the main memory and the data exists on the data bus. This is characterized in that the synchronization signal line is used to start reading of the auxiliary processing device.

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 2 shows an embodiment of the present invention. The CPU9 outputs the internal status display line with the auxiliary processing unit synchronization a<hereinafter AP8.
) has been improved to have 11. AP2 has been improved so that in addition to having APS 11 connected to the status display line 4, address bus 5 and address synchronization 6 are not connected. In this way, there are 3 CPUs and 20 APs.
Books can also reduce input and output bins.

FIG. 3 shows the parts necessary for controlling APZ in the CPUI. The arithmetic unit and the arithmetic control unit are omitted because they may have any configuration.

The instruction code is supplied by data bus 7 and gate 12
The command is set in the instruction register 13 (hereinafter abbreviated as "■") via the command register 13. The instruction is decoded by the instruction decoder 14, and A
It is determined whether the instruction is to be processed at P2 (hereinafter abbreviated as AP instruction). The determination result is notified to the υ microprogram through the signal line 15.

The selector 17 receives the designation of the microinstruction via the signal line 16, and receives the AP instruction tft: in the lR13.

selects internal bus 26 and sends it to output buffer 18.

The value of the output buffer 7 is output to the data bus 7 via the gate 19.

7 lip-flop 20 (hereinafter abbreviated as FF) is APSII
It is used to output a synchronizing signal through gate 21. This FF 20 is set by a signal line 22 and reset by a signal line 23. These signals are specified up to the microinstruction.

Data bus synchronization 8 indicates that the data on the data bus 7 has been finalized or that the data has been stored. cp
When tri receives data from another device, data bus synchronization 8 indicates that the value on the data bus is fixed. When the CPUI sends data to another device, data bus synchronization 8 indicates that the device receiving the data has already stored the data. In either case, the microprogram is informed via gate 24 and signal line 25.

FIG. 4 shows the flow of a microprogram for controlling AP2 using the above circuit.

Here, a case is shown in which two operands are stored in registers within the CPUI.

In step 27, the signal I! indicates whether the command of lR13 is an AP command or not. Look at 15 and decide. If it is not an AP command, the process advances to step 38, where normal command processing is performed and the process ends.

If it is an AP command, the process advances to step 28. Step 28 selects the contents of lR13 from selector 17. output partfu-ylB,
)y'-) 19'e to the data bus 7. Then, j) sets the FF 20 through the signal line 22 and instructs to output to the APS i i via the gate 21e.

Step 29 is a signal! 25t--Check to determine whether Ar1 has received the AP command. If it has not been received yet, proceed to step 39. Here, a time-at judgment is performed. The time foot judgment is a circuit that recognizes a case where no response is returned from Ar1 even after a certain period of time has passed after APSII is set as an abnormal state. If it is not a time act, the process returns to step 29. In the case of a time act, abnormality processing in step 40 is performed and the process ends.

When it is learned in step 29 that Ar1 has received the AP command, the process proceeds to step 30. Here, rA is connected to the signal line 23.
Psllt-Reset.

Step 31 selects the first operand (internal data) to the selector 17. Output buffer 18. It instructs to output to the data bus 7 via the gate 19, and sets APSllt- via the signal line 22.

Step 32 resets pAPSll via the signal line 23.

Step 33 instructs to output the @2 operand (internal data) in the same manner as step 31, and sets APSII.

Step 34 resets the APS 11' via the signal line 23.

Since all the data necessary for Ar1 has been sent above, C
PUI waits for the completion of the calculation of Ar1.

Step 35 sets APs 11 on the signal line 22 and requests the calculation result 't-AP2.

Step 36 checks whether data bus synchronization has been set via signal line 25. If it is not set, return to step 36 and check again. If it is not set, proceed to step 37.

Step 37 instructs to take in the data on the data bus 7 through the gate 12, and sends the data to the signal line 23.
Reset to iAP811.

In this way, a series of CPU-side processing ends.

At this time, if the first operand or the second operand is data on the main storage device, step 31. Steps 33 and 41 to 4 in FIG.
Just change it to 5.

Step 41 shows an operand address calculation procedure used when the CPUI performs a normal main memory read.

Step 42 shows a normal main memory reference procedure performed by the CPU using the operand address calculated in the above procedure.

When referring to the main memory in this way, Ar1 does not need to read the main memory by commonly using the main memory reference procedure normally performed by the CPUI.

Step 43 checks whether data bus synchronization 8 is set on the signal line 25 or not.

If it is not set, the process returns to step 43.

If it is set, it means that the data is fixed on the data bus 7, and the process advances to step 44.

Step 44 sets pAPsl 1 on signal line 22.

Step 45 notifies the main storage device 3 of the end of reading and ends the process.

Ar1 operates in synchronization with the above-described operation on the CPUI side.

Figures 1 and 6 are examples of the interface control circuit of Ar1.

The AP command on the data bus 7 is passed through the gate 46 and set in the AP command register 48. This is instruction decoder 4
9, and informs the p microprogram via a signal line 50 whether the instruction is to be processed by itself or not.

Next, the first operand is set in the first operand register 51 using the logical product (gate 52) of APSII and the output of the FF 57 inverted by the gate 58 as the timing.
Ru.

Similarly, the second operand is the second operand register 53.
is set to

These values are output to internal bus 56 as necessary.

The operation result is set in the result register 55 from the internal bus 56 and output onto the data bus 7 via the gate 47.

APSII passes through gate 59 to gate 52° gate 5
4, etc., and informs it to the p microprogram through the signal line 60.

FF62 is set to p by signal 4163, and signal line 64
It is reset by . These signal lines are excited by instructions from the microprogram.

The output of the FF 62 is outputted via a gate 65 and used as a data bus synchronizer 8.

F and F57 are used to select operand registers.

At the start of processing, the signal 161 is sent as instructed by the microprogram.
It is reset by . Therefore, the output of gate 58 becomes logic MA'''1#, and the first operand register is selected. When data is stored in the first operand register, APS i i is set, so FF 57 is set. Therefore, the second operand register is selected next.

Signal 966 informs the microprogram that storage of operands necessary for the operation has been completed.

FIG. 7 shows the flow of a microprogram that communicates with the CPUI using the above circuit.

Step 67 checks whether APSII is set using the t-signal @60. If it is not set, the process returns to step 67. Step 6
Proceed to step 8.

Step 68 sets the data 'kAP command register on the data bus 7. Then, the instruction decoder 49 decodes the instruction t.

Step 69 checks by signal edge 50 whether the decoded command can be processed by itself. Terminates processing when it is not your command. If it is determined that the command is one's own, the process proceeds to step 70.

Step 70 sets υFF62'e by signal edge 63 and data bus synchronization 81! l-Set. Due to this, C
PUI learns that AP2 has received the AP command.

Step 71 resets the FF 62 using the signal line 64 and resets the data bus synchronization 8.

Step 72 checks the signal line 66t to determine whether all operands necessary for the operation have been stored. If the stored value is not 9, a check is performed at step 72. If it is stored, the process advances to step 73.

Step 73 starts the specific arithmetic processing specified by the AP instruction. When the arithmetic processing is completed, the process advances to step 74.

Step 74 checks whether APSII is set by checking signal @601? :investigate. If it is not set, the CPU has not yet requested the results. Therefore, go back to step 74 and repeat the process. If set, the process advances to step 75.

Step 75 specifies the result from the internal bus 56 to the result register 55. The result is then output onto the data bus 7 via the gate 47.

At the same time, the signal a63 sets j) FF62 and data bus synchronization 8 to notify the CPU that the result on the data bus 7 has been determined.

Step 76 checks whether APSII has been reset via signal line 60. If it has not been reset, the CPUI has not yet stored the results, so proceed to step 7.
Go back to step 6 and repeat the p check. If it has been reset, proceed to step 77.

Step 77 finishes outputting the result onto the data bus 7, resets the FF 62'i via the signal line 64, and resets the data bus synchronization 8.

With this, the series of processing is completed. The example described here is a case in which AP2 uses two operands, and it is clear that similar processing can be performed in other cases as well. For example, if there is one operand, steps 33 and 34 in FIG. 4 may be omitted. Accordingly, in step 72 of FIG. 7, the logic output to be checked may be inverted.

As described above, it can be seen that according to the present invention, only one signal, APSII, is required to be added in order for the CPUI to control the AP2. Furthermore, AP2 no longer needs to incorporate address bus 5, address synchronization 6, etc. Although this example shows the case where the address bus 5 is 16 bits, the number of bits will increase from 24 to 32 as the address space is expanded in the future. In times like these, the present invention is even bigger! !
It brings about a great effect.

Furthermore, according to the present invention, even when there are a plurality of APs 2, it is possible to expand without making any changes to the circuit.

FIG. 8 shows an example of this case. In this example, N units (N
is a positive integer) is connected to the CPUI. AP2-1 is the first device, AP2-2 is the second device, and person P2-N is the Nth device. In the figure, the AP and main storage device in the middle are omitted. APSII can be wired logic as shown in the figure. All commands processed by each AP are exclusive, so only one responds with data bus synchronization 8 to nine AP commands sent from the CPU.
There are only two APs. Further, if all APs do not respond, the CPUI can know that there was no response due to the abnormality processing at step 40 in FIG.

According to the present invention, the following effect t6 can be achieved.

1. The central processing unit and the auxiliary processing unit can synchronize the transfer of instruction codes and operands using only one signal line, and the arithmetic processing of the auxiliary processing unit can be started. Furthermore, it is possible to know the storage of results and the end of arithmetic processing.

2. The auxiliary processing unit can transfer operands without having an address bus or input/output pins for address synchronization signals.
Results can be stored.

3. A plurality of auxiliary processing devices that perform exclusive instruction processing can be expanded without changing the circuit.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing a conventional microprocessor, FIG. #I2 is a diagram showing a schematic configuration of an embodiment of the present invention, FIG. 3 shows the flow of the microprogram that drives the circuit shown in FIG. 3. FIG. 5 shows a partial modification of FIG. 4. FIG. Figure 7 shows the flow of a microprogram that drives the circuit shown in Figure 6, and Figure 8 shows an example of expansion of the auxiliary processing device. 1...Central processing unit, 2...Auxiliary processing unit, 7 river data bus, 2...Data bus synchronization, 11...Auxiliary processing unit synchronization, 20...Flip 70 for auxiliary processing unit synchronization signal , 62...Slip a for data bus synchronization signal
1 figure darkness 3 figure? 1−−−−−−−−−=−−−−−,
J porridge 5 Figure 1 Yumi Otsu “So”

Claims (1)

[Claims] A central processing unit that constitutes a microcomputer system, an auxiliary processing unit that processes instructions other than those processed by the central processing unit, and a main memory that stores the instructions and data necessary to execute the instructions. In an information processing device having a path for transferring addresses and data between a central processing unit, an auxiliary processing unit, and a main memory, the central processing unit transfers instructions or data to be processed by the auxiliary processing unit to the path. A synchronization signal I11! is sent to the auxiliary processing device when data is sent to the above path or when data is requested to be sent onto the path. i-, the auxiliary processing unit receives the instruction or data on the path in response to the synchronization signal, or sends the requested instruction or data on the path. An information processing device comprising a circuit.