JPS58117723A - Digital-to-analog converter - Google Patents

Abstract

PURPOSE:To attain high accuracy with a simple construction, by providing a bit having the same importance as the most significant bit and guaranteed for the linearity duplicatedly and using this duplicated bit as a correction bit. CONSTITUTION:A 16-bit digital input signal applied to an input terminal 12 is divided into the upper-order 11-bit and the lower-order 5-bit X. The upper-order 11-bit is converted into a correction code at a code converter 18 to be the upper- order 11-bit 16b of a D/A converter 16. The code converter 18 outputs a correction signal Y to the lower-order 5-bit in addition to the control output to duplicated bits A, B, and the signal Y and the lower-order 5-bit X are summed at an adder 17. The output of the adder is the lower-order bit 16a for the D/A converter and when carry comes from the adder, the output is summed to the upper-order bit as a carry signal CY.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a DAA conversion device, and in particular, it is possible to obtain a DAA conversion device with high accuracy even when integrated into an IC.

<Background of the Invention> A DAA conversion device generally comprises a resistance ladder circuit l of resistors having a resistance ratio of R-2R, as shown in FIG.
A constant current source 3 is connected to each branch point of this resistance ladder circuit 1 through switches 41 to 4n that are turned on according to a digital value, so that an analog output is obtained from an end 5 of the resistance ladder circuit. Conversion errors occurring in a DAA converter having such a configuration largely depend on the accuracy of the resistors forming the resistance ladder circuit 1. Conventionally, the resistance ladder circuit 1 is formed of a thin film or the like, and variations in resistance value are corrected by laser trimming or the like to obtain a DA disguise device with a predetermined accuracy.

By the way, when the DAA converter is integrated into an IC, there is no means for correcting the resistance values of the resistors constituting the resistance ladder circuit 1. Therefore, in implementing the DAA converter into an IC, it is necessary to find a method for correcting conversion errors without correcting the resistance values of the resistors constituting the resistor ladder circuit 1. For this reason, a type A converter shown in FIG. 2 has been proposed. The ODA converter includes weighted constant current source groups 6a, 6b, and 6c, switch groups 4a to 4n that are controlled on and off by digital input values, and weights for the output currents of the constant current source groups 6b and 60. The resistor circuits 7a and 7b and the buffer amplifier 8 constituting the current adding circuit are constructed in a similar manner to minimize the number of resistors.

The trick circuit configuration reduces problems caused by variations in resistors. However, there is a drawback that variations in the characteristics of the transistors constituting the constant current source cause variations in the current value, and a conversion difference occurs due to the variation in the current value.

<Conventional Description> A conventional example of correcting the conversion error of the DA converter without modifying the resistor or the current value of the constant current circuit is shown in FIG. is the main DA
A transducer is shown. A digital value to be converted is inputted to the main DA converter 11 from an input terminal 12, and the converted output is outputted to an output terminal 13 via a buffer amplifier 8. 14 is an auxiliary DA converter. This auxiliary DA converter 14 is
The A converter 11 has the number of digits corresponding to the analogue quantity, and outputs an analog quantity equivalent to the error of the main DA converter 11 and adds it to the input side of the buffer amplifier 8. It works to correct. The error of the main DA converter 11 can be predicted in advance based on the accuracy of the resistor rutter circuit 1 or the constant current circuit 68 to 6C, or can be determined in advance by actual measurement, and the data for correcting the error can be stored in the ROMI 5. I'll leave it there. The data in the ROM 15 is read out based on the digital input value, and a correction amount for the error is output from the auxiliary DA converter 14 to the digital input value, thereby correcting the error of the main DA converter 11.

<Conventional disadvantages> The conventional method for correcting a DA converter is to provide an auxiliary DA converter 14 and output the error phase at of the main DA converter 11 from the auxiliary DA converter 14.
This requires a large number of digits in the converter 14. Therefore, there is a drawback that the cost is measured.

Object of the Invention The object of the invention is to provide a DA converter having the simplest structure and capable of correcting errors in a DA converter.

<Summary of the Invention> In the present invention, at least the most significant bit within a range where linearity can be guaranteed is provided redundantly, and the redundant bits are used to correct errors in the DA converter. Therefore, according to the present invention, for example, in a DA converter having a capacity of 16 bits, errors in the DA converter can be corrected by simply providing duplicate bits of about two digits. Therefore, a highly accurate DA converter can be obtained at low cost.

<Structure and operation of the invention> FIG. 4 shows an embodiment of the invention. In the figure, 16 indicates a DA converter. In the present invention, an overlapping bit is provided in the DA converter 16 at least in the most significant bit within the range where linearity is guaranteed. The range in which linearity can be guaranteed will be explained in detail later, but the range in which linearity can be guaranteed is
In general, linearity is guaranteed up to the bit consisting of the LSB. Here, the range from the least significant bit to the 5th bit is assumed to be the range in which linearity can be guaranteed. Therefore, a duplicate bit A is provided at the fifth bit from the lowest. The setting of this duplicate bit A is as follows.
In both Figures and Figure 2, constant current sources and switches are provided redundantly,
Resistance ladder circuit 1 is created by superimposing the currents of each constant current source.
Alternatively, it may be configured to flow through the resistance circuit 7a or 7b.

On the other hand, in this example, the 8th bit from the lowest is also the duplicate bit B.
An example is shown below. For this 3i multi-pitch) B, the constant current source and switch for the 8th bit may be provided redundantly in the same way as described above.

The digital value to be converted supplied to the input terminal 12 is the lower 5
The lower 5 bits are supplied to the lower 5 bit digital input terminal 16m of the DAF converter 16 through the digital adder 17. The upper 11 bits of the digital code are supplied to a code converter 18. This code converter 18 can be configured by, for example, a ROM. The code converter 18 converts the input digital value into a correction code obtained by adding a correction value corresponding to the error value held by the DA converter 16, and converts this correction code into D.
The upper 11 bits of the A converter 16 are connected to the input terminals 16b and the input terminals 16c and 16 of the A and B input terminals 16c and 16 overlap if necessary.
Give to d. In addition to the control output for the overlapping bins A and B, the code converter 18 outputs a correction signal Y for the lower 5 bits whose linearity is guaranteed. This correction signal Y and the input value X of the lower 5 bits are added by an adder 17, and the addition result is supplied to the input terminal 16a of the lower bits.

At this time, if the added value overflows, carry signal C
It is added to the upper bits at y.

In the above configuration, assuming that the linearity of the lower 5 bits is guaranteed, the lower 5 bits can be used freely by adding duplicate bits, such as ``person'', to the bit where an error occurs among the upper 11 bits. can be put into a state where it is possible. In other words, in a digital input value that selects the upper 11 bits and further selects the lower 5 bits, first of all, if the jDDA conversion output deviates from the ideal value to the positive side due to the digital input value, then by changing the combination of the upper bits, The combination of upper bits is changed so that the output side generates an error that deviates to the negative side from the ideal value. At this time, the selection of the lower 5 bits can be separated by adding duplicate bits A or B. Then, by adding A or B and selecting a combination of high-order bits so that the value is slightly less than the ideal value, and then adding the lower bits appropriately, it is possible to approach the ideal value. . By using the lower 5 bits, the adjustment step for approaching the ideal value 1z can be adjusted in ILSB steps, and the combination of bits that generates the analog output closest to the ideal value is stored in the code converter 18 in advance. It is something to keep. As a result, analog errors can be corrected in ILSB steps over the entire range using the lower 5 bits.

Effects of the Invention> Therefore, according to the present invention, the range of correction of the analog output value can be expanded with a simple configuration.

Furthermore, since the value of the circuit resistor is not changed, it can be easily integrated into an IC. In particular, since it is only necessary to provide about two overlapping bits, the structure is simpler than in the case where the auxiliary DA converter 14 (FIG. 3) is provided, which is effective in reducing costs.

<Detailed Description of the Invention> Next, the reason why the lower bits described in the above-mentioned embodiments have linearity and errors occurring in the DA converter will be explained.

If the analog output voltage corresponding to each bit of a general binary DA converter is V o -V n % and the error with respect to its ideal value is EO - En, then the output voltage for a certain combination is vi for each bit. If the ideal value is summer (Vi+Ei) (1)
Kura is the sum of the analog outputs of the bits that are turned on, and i is the bit honor code.

If the full-scale voltage of the DA converter is V, then in order to guarantee true linearity, a DA converter with n-bit resolution is required.
In f chivalry, IJ(Vi+Ei)-JVi l<V'2-(n")
(It must be 21. This second equation means that for each gage digital input, its converted output is 1!
- This means that it must be less than or equal to the LSBO value. By the way, Vi=V・2(i-n-t) Ei=vi11Pi (Pi is the error rate of bit i, the error rate of the element using the pick) Therefore, 1'(1+Pi)2("-")-m2( i-n-1)
1<2-(n+t)l XP i * 2 ('-n-
')l <2-('''') (31, that is, the formula that guarantees linearity in normal DA
If L has a uniform variation width for all bits, even if the third equation does not hold true for all bits, L
Depending on the conditions of Pi, the third equation partially holds true over several bits from SB.

For example, when 1Pil<0.01 n=15, and under the worst condition Pi=0.01 (excluding upper bits), the third equation is P i @ , J 2(1-n-") < 2- (n
+ri (4)1-(1, and there must be a K that satisfies this, Pi=0.0
2 in 1 z 2 (i-H-Q=2-(B+1), (2x+x g
l-.

++... 24. @shin@", 2-(n"), (2+1 1X z-(n+t)2 ≤2+1, °, ≤4 Therefore, true linearity is guaranteed for the change in the lower 5 bits. However, as shown in Figure 5, linearity cannot be guaranteed at all for all bits, but if only the lower 5 bits change, linearity and linearity cannot be guaranteed at any point.
Monotonically increasing property can be guaranteed.

\, and considering again the condition of IPiI≦0.01 -15, each point on the solid line in Fig. 4 is calculated from equation 1, and the analog output Va is Va = = J (Vi + Ei) (
51 error is E = ΣEi = VX 2 (''-1)・P i
(6) Equation 6 includes the full scale error. The equation that normalizes the full scale and expresses only the linearity error is:
It can be derived as follows.

■ 已120-”-”(1+Pi)-1+2-(””)1
−.

Linearity error EL is 1... EL = □Σ (Vi + Ei) - ΣVi 1 + ΔK (8) EL: error when turning on any bit, MSB,
When only one bit is on, from the above equation, when P1m=Δ, EL=0 when Δ=O1 and pts=o. In other words, ΔK is small, and Et, whose P eye is a dog, is large.

In the general case, the linearity error can be estimated by equation 8. In this case, the maximum value of EL is: pss = 0.01 P s < = -0,01 P1m = 0.01 P1 -0,01 pl = 0.01 P o = -0,01 In this case, Σ: Bits 15, 13, 11. ...-1 is on Substituting these into the 8th equation, EL=4.43
The linearity error Er, is approximately ±0.44% at maximum.

As in the above example, if the error/difference of the parts used is 1 inch, the D
In order to correct the linearity of the A converter over 16 bits, it is possible to add a DA converter with an output of ±0.44% for correction, as shown in Figure 3, but it is redundant and is preferable. do not have.

Therefore, in this invention, if we focus only on the upper 11 bits, the error must be within ±0.44 bits, and if we assume that linearity is guaranteed for the lower 5 bits, then the upper 11 bits can be used for 2048 types. It has a step, and its valley value may deviate from the ideal value by up to ±0.44%. If this error can be kept within -0,048%, the lower 5 bits can be used to correct the vicinity of the ideal value using the ILSB step.

Further, by preparing a duplicate bit A having the same value as bit 5, the ILSB resolution can be maintained until the next step (the upper 11 bits).

By the way, the upper 11 bits are ±0.44% to -0,
This is a method to achieve accuracy within 0.97%, but consider cases where the output value is higher and lower than the ideal value.

(B) When low: Two bits 4 to 7 when bits 4 to 8 are not turned on.
This can be corrected by turning on.

When bits 6 to 8 are insufficient: Provide a superimposition bit B, which is the same as bit 8, and turn it on to combine bits 4 to 7.

(b) If it is high: Select the value one step lower. Then maximum -0,54
There is an error of -, but it can be adjusted in the same way as (a).

As explained above, in this invention, a duplicate bit is provided at least in a bit that has the same weighting as the most significant bit within a range where linearity can be guaranteed, and if necessary, a duplicate bit is provided in an even more significant bit, such as the 8th bit. By combining these overlapping bits with bits in the range where lower linearity is guaranteed, the output value can be corrected over the entire range. Therefore, it can have a simple structure and can be manufactured at low cost. Moreover, since the characteristics of the X element constituting the circuit are not modified, a highly accurate DA converter can be obtained even when integrated into an IC.

In the above description, the ROM 18 is configured to perform the operation of converting the input digital value into a corrected digital value.
RAM can also be used.

Furthermore, in the above example, the duplicate bits were provided at the 5th and 8th bits from the lowest order. However, the selection of the duplicate bits is determined by the error rate of the elements constituting the DA converter 16, so It is easy to understand that this is not something that can be determined based on the above, and therefore it is not limited to the above-mentioned example.

[Brief explanation of the drawing]

Figures 1 and 2 are connection diagrams for explaining the circuit structure of a generally known DAK converter, Figure 3 is a block diagram for explaining the correction method of a conventional ODA converter, and Figure 4 is a FIG. 5, which is a block diagram showing an embodiment of the present invention, is a graph for explaining the correction method of the DA converter according to the present invention. 12: Digital input terminal, 16: DA converter, 16c
, 16d: Duplicate bit input terminal, 17: Adder, 18
: Code converter. Patent applicant Takeda Riken Kogyo Co., Ltd. Agent Kusano
table

Claims (1)

[Claims] (1) A DAA conversion device in which a bit having the same weight as the most significant bit within a range where linearity can be guaranteed is provided redundantly, and the redundant bit is used as a correction bit.