JPS58115958A - Exchange control system - Google Patents

Abstract

PURPOSE:To offer an exchange control system for a multi-processor unit system which can connect many line control systems efficiently, without remarkable reconstruction of the hardware, by providing a virtual input/output buffer memory for a common memory. CONSTITUTION:An ROW called from a line A is picked up from an IB0 by a CPU0 for call reception processing. Assuming that a called party X recognizes to be connected with a line B of a CCU1. The CPU0 rewrites a TSN-CPU No conversion table 43 provided corresponding to a TSN (channel address) of the line B so that it is indicated that the TSN on the line B is controlled with the CPU0. Further, the CPU0 sets an ORW for the start to the line B to a block on a virtual OB42 corresponding to the CCU1. The CPU1 monitors whether or not the ORW exists in the block corresponding to the CCU1 on the virtal OB42 periodically, and when exiting, the ORW is copied to the block corresponding to the IMOB42 on an MM. The CPU1 picks up the ORW copied from the IMOB42 with the IB/OB switching instruction from the CPU1 and controls the start of the line B.

Description

DETAILED DESCRIPTION OF THE INVENTION (1) Technical Field of the Invention The present invention relates to a switching control system, particularly to a switching control system suitable for application to a telex network.

(2) Technical background As an exchange device for telex, etc., the 11iii! So-called electronic switching systems, which have four components: a control device, a central control device, and a master control device, are rapidly becoming popular. In this case, if the line network standard or IA is small, at most one series of the above-mentioned components is sufficient.

However, as the scale increases, it is no longer possible to handle it with just one line. For this reason, it becomes necessary to adopt a so-called multigrossing unit system format. In other words, several sets of line control systems each consisting of a central rfjlh distribution device, a main device, and a line control device are not provided in parallel. These multiple sets of line control systems are closely coupled to each other in terms of line switching. The quality of exchange control depends on how efficiently this tight connection is executed.
It is also a deciding factor. Note that a common memory 'r is usually provided to organically connect d sets of line control systems. The present invention primarily refers to such organic linking techniques.

(3) Prior Art and Problems FIG. 1 is a block diagram showing an example of the configuration of a conventional key exchange system. In this figure, 1o.

Reference numerals 11 and 12 represent each of the plurality of sets of line control systems described above. However, the case of three sets is shown. Each line control system has a similar configuration9, and has a large number of line termination units (CTUs) connected to a large number of subscriber lines or trunk lines to other stations.
) 13, a line control unit (CCU) 14 that centrally controls a large number of CTUs, a central control unit (CPU) 15 that controls the CCU, and a request word (RQW) and Main memory (MM) that sends and receives order words (oaw)
It consists of 16. A common memory (CM) 17 is provided to organically connect the line control system 10 having these configurations to the other line control systems 11 and 12.

FIG. 2 is a schematic diagram showing basic exchange control operations and main turns in each line control system in FIG. 1.

Reference numeral 21 in the figure is a circuit #rtilJ, which connects to another person or other stations 22, 22'. Symbol F in the figure is a line in the forward direction (3), and symbol B is a line in the backward direction (back).
ward) line. The signal shearing performed in these forward inner concave @F and reverse self-circulation -B is shown as a vertical flow in this figure, and A and 2 are the so-called A polarity and bipolar. 〇 Various signals The generation timing is as shown in the diagram.■ Calling signal (or activation signal) CLL ■ ss reception ready signal PTS ■ Selected digit signal SS ■ Call confirmation signal CID ■ Called answer signal OLD -AAB ■ Disconnection signal CLR ■ Disconnect confirmation symbol According to the CLR-CFM sequence.

On the subscriber 22' side, Who are you anonymous code W?
R.U.

The activation confirmation signal CLL-CFM etc. rises.

Figure 3 shows the relationship between any two line control systems in Figure 1.
5 is a time chart showing a typical example of a transmission procedure performed via a common memory CM. In (4) of this figure, the dself signal similar to that already described is a signal having the same function. Therefore, to explain the symbols that appear for the first time in this diagram, CH is a character, LVSNDA
is A pole transmission, LVSNDZ is 2 pole transmission, 5NDPLZ is 2 pole i4h transmission, LVRCVA is A pole reception, LVRC
VZ is 2-pole reception, MOD is mode change order, M
ODo is a through mode, and MODI is a monitor mode. Note that since FIGS. 2 and 3 are conventional examples of signal sequences, detailed explanations will be omitted.

By the way, in the conventional electronic switching system mentioned above, the CCU
The above RQW setting light can be used with any CPU-compatible MM,
Especially the MM person's Kabuffa memo! I had to decide whether to allocate 9 to J (IB) and perform some operations to determine the allocation. Therefore, each CCU has R
A dirt circuit was provided to distribute the QW report destinations, and the above-mentioned distribution was carried out through this. However, the line control system (10
, 11, 12) is fine if the bulk is about 2 cm, but
When this was expanded to three or more sets, a problem arose in that the dirt circuit described above became complicated and large, making it uneconomical.

(4) Purpose of the Invention In view of the above-mentioned conventional problems, the present invention provides a multi-gross controller unit that is capable of efficiently and organically connecting a large number of line control systems without significantly modifying the hardware. The purpose of this paper is to propose a switching control method for the system.

(5) Structure of the Invention In order to achieve the above object, the present invention focuses on the conventional common memo 90-capacity VC, which merely handled common control information between CPUs, and the CM includes a virtual human buffer memory and A virtual output buffer memory is provided, in which the request word RQVV and order word ORW corresponding to each CPU are temporarily stored. The feature is that it is performed on the output/9 file memory and searches for the RQvV and 0FtWf necessary for the self.

(6) Examples of the invention The present invention will be explained below with reference to the drawings.

FIG. 4 is a block diagram of an electronic switching system used to explain the present invention in detail. In this figure, 44,4
5. Blocks 46 and 47 are shown in Figure 1.
．． 15.16 and 17, and there is no change in the basic configuration. In addition, the above-mentioned input cover, Fa Memory (IBO
+ IBL * IBI) are the corresponding MM,
, MM, , m, as before. Output buffer memory for this (0B(1+OB
s*OB2) are also IBo.

IBl* MMo, MM that corresponds to IBl
l.

It is conventionally provided within the MMl. Therefore, virtual input buffer memory (IMIB) 41, virtual output buffer memory (IMOB) 42 and table (TBL)
43 is the newly introduced block,
As shown in the figure, it is provided in a common memory (CM) 47.

In the configuration shown in FIG. 4, the actual size buffer memory (IB) and actual output buffer memory (OB) in the vehicle storage device MM will be mentioned. These correspond to the aforementioned virtual input and output buffer memories (IMIB, IMIO) and are existing ones.

(7) FIG. 5 is an array diagram showing the configuration of the actual size buffer memory and the actual output buffer memory in each main memory device MM in FIG. 4, and includes the CCU, #CCU, . . .
and the nth (up to n = 3 in Figure 4) CCU
Area CCU Yu corresponding to n. ,C Chiang,...CCU,
Two input buffer memories IB and two output buffer memories OB are arranged every n.・For each IB,
There are two sides like O2÷01, and similarly for each OR, O
There are two such as O1φ01. This is a well-known method for efficiently transmitting and receiving data, and is intended to perform parallel operation in which the previous data is simultaneously read out while new data is being imported to one side. However, this does not relate to the essence of the invention. In addition, per page (I
Regarding B) 16 CLLs (calls) can be stored at a time.

Figure 6 shows table 4 in the common memo 90M in Figure 4.
3 is a slightly more specific diagram. This table 43 is T
It should be called the SN-CPU A conversion table,
9. TSN is an abbreviation for time slot shop (8), and is also a so-called channel address. Figure 7 is the 4th
Figure 8 is a slightly more concrete version of the virtual manual buffer memory (IMIB) 41 in the common memo 90M shown in the figure.
FIG. 4 is a diagram slightly specific to the virtual output buffer memory (IMOB) 42 in the shared memo vCM shown in the figure. The virtual human cover and family memory 41 shown in FIG. 7 are compatible with each CPU (CP
U, the following are not shown), each C for each CPU
RQW which is input data from CU (CCU6, CCUl-CCU,) (CCUn is n=3 in Fig. 4)
Ba, Fa once. The virtual output buffer memory 43 in FIG.
CUn) (in FIG. 4, n=3 for CCUn), the order word 0 is temporarily buffered.

Although it is compatible with the CCU, it actually has no compatibility with the CPU. First, let me explain about these request words RQW and order words ORW.
This is illustrated in Figure 1. Figure 10 shows the request word R.
FIG. 11 is a layout diagram showing an example of the configuration of the order word ORW. In Figure 10, the 16-bit word is the first word.
It consists of a word and a second word, and the first word has RQC (
The request code) and Address' (the above-mentioned time slot shop) are stored, and the second word is the data (D
ata). This is detailed data for request code RQC. In the il1 diagram, for example, a 16-bit word consists of a first word and a second word.The first word stores ORD (order code) and Address (time slot A), and the second word stores data. ).

This is detailed data for the order code.

IMIB, IMOB, TBL mentioned above,
A series of operation examples related to RQW, ORW, etc. are shown in Figure 9A~
This is illustrated in Figure 9■.

9th A, 9B, 9C, 9D, 9th, 9F, 9G.

9H and 9H are schematic diagrams used to break down and explain an example of the operation according to the present invention over steps 1.2, 3.4, 5, 6.7.8 and 9. These 9th A~
The operation example shown in Fig. 9I is quite concrete, and before going into details, I will explain the basic concept a little more. In other words, the virtual person buffer memory MIB2 and the virtual output buffer memory IMOB are used by all CPUs (CPU
g, CPU+ -), and each line CPU processes the RQW belonging to the line control system by itself, while on the other hand, the RQWk belonging to another line control system corresponds to the other line control system. I do
MIB, and each CPU processes the snore W belonging to the line control system by itself, while conversely, the ORW belonging to another line control system is processed by the IMOB corresponding to the other line control system. Each line CPU periodically collects (searches) the contents of the IMIB and IMOB corresponding to itself. The control flow is roughly as shown in 9 below. The RQW of the line ■ (bottom of Figure 4) is called by CPU0 from IB,
Performs call reception processing.

Next, the selection signal of called party X (
Code) SS RQW 'e is received. This SS
As a result of the analysis, it is assumed that it is found that the called party X should be connected to CCU 1 through line ■ (11).

However, the CCU cannot directly access the line (2) of the CCU (this is conventional).

Therefore, the CPU rewrites the TSN-CPU I& conversion table 43 provided for the T8N (channel address) of the line (2) to indicate that the TSN of the line (2) is controlled by the CPU. Also, CPU.

is the ORW for booting to the line ■ cct on the virtual OB
■Set in a block compatible with 1. On the other hand, the CPU.

periodically monitors whether or not there is an ORW in a CCUI-compatible block on the virtual OB (IMOB), and if the ORW is missing, it is transferred to the corresponding block in IIVIOB of MM-L.

The CCU takes out the snore M transferred from the IMOB in accordance with the IB, 08 screen switching command from the CPUI, and performs activation control for the line ■.

Also, the RQW in response to this activation is from CCU 1 to I
It is set to B. CCU 1 receives this RQ as described above.
The TSN of W is extracted, and based on the TSN-CPU conversion table, the CPU that should control this RQW is CPU.
0(12), CPU0 sets this RQW to the block on IMIB to be searched.

Similarly, CPUo periodically searches the corresponding block of IMIB for the presence or absence of RQW, receives 'RQW from CCU via IMIB, and further performs normal internal connection processing based on this. Let it proceed. Note that the above-mentioned periodic search (activation) is performed at intervals of approximately 10 ms. FIGS. 12 and 13 summarize the above operations in detail in the form of flowcharts.

Figure 12 is a flowchart showing an example of the request word RQW setting sequence, and Figure 13 is the order word OR
3 is a flowchart showing a setting sequence string of W. In addition, the SOW in FIG. 13 is 80urelloof or
It means der word (0RW).

As already mentioned, FIGS. 9A to 9I show two operational examples, which will be explained step by step.

Beg for it! j1 (Figure 9A) (1) When receiving Z (ffi) continuously for 10'Oms from the Karo line, the CCU reports an RQW (Request word) of call detection to the CPUO.

(2) The CPU allocates time slots (TSN) to subscriber lines and also controls the time slots.
Let PU be CPU0 (TSN-CPU A conversion table).

1:3) CPUo sends PTS (
ORW (Z original pulse transmission)
) and sends it to CCUo. (4) The CCU receives this and sends 2 poles and 9 pulses to the subscriber line.

O f-, f2 (Fig. 9B) (1) , , jJI receives the selected number (SS) of the one-person artificial line subscriber from CCUo and stores it in ■.

(2) The incoming subscriber is determined based on this SS, and when it is determined that this is a vn person accommodated in the CCU, the time slot of CCU 1 is hunted, and the control CPU of this time slot is TS that it is CPUo
Set on the N-CPU A conversion table.

(3) Set the activation order ORW to the called subscriber in the virtual OB area on the CM.

Separately from this, a call confirmation signal (date, call acceptance number) f: is sent to the caller vn person.

Stella υ (Figure 9C) (1) The CPU increases the ORW set by the CPU in step 2 (3) from the virtual OB area and sends it as is to the CCU.

(2) In response to this, the CCU1 changes the line status of the terminating subscriber line to bipolar.

Step 4 (Figure 9D) (1) When the subscriber line responds to step 3 and the line status changes to bipolar, CCU 1 reports the RQW of bipolar reception to the CPU.

(2) The CPU receives this and determines the control CPU based on the time slot number included in this RQW, and if it finds that this is CPU o, it sets the virtual IB of CPU o.
Set Heko's reception RQW.

Step 5 (Figure '9E) (1) Virtual I for RQW k CPUo in step 4
When the CCU finds that the eject activation confirmation signal has been returned from the B Elite, the WRU is sent to the incoming person who is being accommodated in the CCU.
Sends a signal (character (C) I) 2 characters) (
15) Set in the CCU l area of the ORW'r virtual OB area.

(2) Also, sends an order (ORW) to the CCUo to set the originating side time slot tray through mode and an order (ortw) to send a CLR detection report (RQW) to the CPU.

Similarly, for CCUI Vc, the called side time slot (
Set an order (ORW) to set the A/B signal to monitor mode in the virtual OB area.

Stella! ”-(Figure 9F) (1) CPU is ORW from CPUo to CCU
(Ken U signal) is taken out from the virtual OB area and the CCU
Send to l.

(2) In response, the CCUI sends W to the incoming line.
The RU signal (two characters (CH)) is sent out in sequence.

(3) Also, retrieve the order to set the incoming call example time slot of CCU1 to monitor mode from the virtual OB area.
1-\Send. This causes the CCU to set its (16) time slot to monitor mode.

Step, Gua (Figure 9G) (1) CCUl is Answer@r from the receiving subscriber.
The CPU uses one character of the back signal (AAB) as RQW.
, report to.

(2) The CPU indicates that this RQW is under the control of the RQU and TSN-CPU.
Based on the A conversion table, set the RQW to the virtual part area corresponding to the CCU1 of the CPU.

(3) CPUo receives RQW from the virtual IB area (
(character information) is stored for one character (because AAB is being received)
, When this is completed, it is checked whether AAB is normal or not. Note that at this time, the received AAB is transferred between CCU1 and CCU (1).

Step 8 (Figure 9H) (1) When AAB is received normally, CPUo Fi
Set the ORW in the temporary 5OA area to change the mode of the time slot on the receiving side of CCU1 to through mode.

(2) The CPUI retrieves the above-mentioned ORW from the virtual OR and sends it to the CCU.

In response to this, ccut changes the called side time slot mode to through mode.

(3) The originating subscriber and the terminating subscriber are now in a communication mode, and can communicate without going through the CPU.

2 Te, G 9, (Fig. 91) (1) When a continuation of A polarity is received from the invented subscriber line, C
CU reports the RQW of CLR signal reception to CPUo.

(2) In response, the CPU uses CL as a confirmation signal.
It edits the R-CFM onwt and sends it to the CCU.

(3) Also, CLR for the incoming subscriber accommodated in CCUl.
Edit the order for sending the signal and set it to the virtual OB area corresponding to CCU 1.

(4) CPU1 reads 0RWtl of CLR from virtual OB.
- Take out and send to CCU1. ,5゜(5)
CCU, is the A pole (CLR-CFM) from the terminating subscriber.
) to CPU5, and the CPU sends this RQW to the virtual I corresponding to CCU 1 of CPUo by T8N of RQW.
Set to area B.

(ft) CPUI is virtual In RQW (CLR-
CFM) confirms that the call has been disconnected, and releases the hunted resources (time slots).

(7) As described in detail, according to the present invention, the line control system (C
A replacement control method is realized that allows for easy expansion of PU, CCU, MM).

[Brief explanation of drawings]

Fig. 1 is a block diagram showing a configuration example of a conventional electronic switching system, Fig. 2 is a schematic diagram showing basic switching control operations and main turns in each line control system in Fig. 1, and Fig. 3 is A common memo I between any two line control systems in FIG.
A time chart showing a typical example of a transmission procedure performed via JcM, FIG. 4 is a block diagram of an electronic exchange system used to explain the present invention in detail, and FIG. 5 shows each main memory device MM in FIG. FIG. 6 is an array diagram showing the structure of the real-sized cover area buffer memory and the real output buffer memory in the memory, FIG. 6 shows the table 43 in the common memo 90M in FIG.
Figure 7 is a slightly more specific diagram of the common memo 90M of Figure 4.
FIG. 8 is a slightly more specific diagram of the virtual person buffer memory (IMIB) 41 in the internal memo 90M shown in FIG. 4. Figure 9A is a slightly more specific illustration of j(IMoa)4z. 9B, 9C, 9D, 9, 9F, 9G, 9H and 9,
Figure 1 shows an example of the operation according to the present invention in steps 1, 2, 3.
4.5.6, 7.8, and 9. The schematic diagram used to explain the breakdown, Figure 10 is the request word RQ.
FIG. 11 is a layout diagram showing an example of the configuration of order word ORW. FIG. 12 is a flow chart showing an example of the setting sequence of request word RQW. FIG. 13 is a layout diagram showing an example of the configuration of order word ORW. 3 is a flowchart showing an example of a setting sequence. 10.11.12... Line control system, 41... Virtual person buffer memory, 42... Virtual output buffer memory, 43... Table, 44-0.44-1.44-2
-HaNIJ at (CCU), 45-0.45-
1° (20) 45-2 ... Central control unit 1 (CPU), 46-
0゜46-1.46-2...Main memory (MM), 4
7...Common memory. Patent Applicant: Fujitsu Limited '4 Patent Attorney: Akira Aoki, Patent Attorney, Kazuyuki Nishidate, Patent Attorney: 1) Yukio Patent Attorney: Akira Yamaguchi, Patent Attorney: Part 12 Figure 13 Procedural amendment document November 30, 1980 Kazuo Wakasugi, Commissioner of the Patent Office 1, Indication of the case 1981 Patent Application No. 213400 2, Invention name exchange control system 3, Person making the amendment Case Relationship with Patent Applicant Name (522) Fujitsu Co., Ltd. 4, Agent (3 others) 5. Column 6 of “Detailed Description of the Invention” in the specification subject to amendment, “Invention Please correct the "Detailed explanation" column as follows. (2) @page 8 @ line 19r (IMIB, IMIO)" to r(IMIB, IMO
B) Correct J. Ge〉 Page 10 If! Correct the 11th line as "Buffer memory 43J'ir back memory 42". (tsu) @Page 12, line 1 o rOPWJThroRwJ and m positive t, tt-0 (-[
3. Correct the date on page 13, line 3: "(It is conventional), Jtr (It is conventional)." (3) On page 17, line 18, ``Incoming call example'' is corrected to ``Receiving party.'' ■ On page 18, line 7, change rRQUJ to rRQWJ. I'N Page 19, wI, line 7, "inventing subscriber (b) line" is corrected to "originating subscriber line". (3)

Claims (1)

[Scope of Claims] 1. A line control system that includes a line control device, a central control device that controls the line control device, and a main storage device that is connected to the central control device and sends and receives predetermined data. The main storage device in each line control system includes a large-capacity buffer memory that accommodates all request words transferred from the line control device, and an output buffer memory that accommodates order words to be sent to the line control device. and a common memory that stores information for common control between the plurality of sets of line control systems, wherein the common memory includes the human buffer memory and the output terminal. A virtual human-powered buffer memory, a virtual output cover, and a virtual memory corresponding to the cover and the firmware are provided, and the virtual human-powered buffer memory, the virtual output cover, and the firmware can be commonly accessed by all the central control units, and each of the central While the control device itself processes the request word that is lost in the line control system, conversely,
Request words belonging to other line control systems are set in the virtual input buffer memory corresponding to the line control system of the function, and each central control unit processes the order words belonging to the line control system by itself. On the other hand, conversely, order words belonging to other line control systems are set in the VT and memory output rough memory corresponding to the line control system of the function, and each central control unit sets the order words corresponding to its own. Virtual input buffer and virtual output buffer r't'' the human buffer memory and A
fJ An exchange control method characterized in that it is handled like a distribution output buffer memory.