JPS58115690A - Read-only memory device - Google Patents

Abstract

PURPOSE:To reduce power consumption and increase operation speed of a read- only memory device which stores information according to the absence/presence of an insulating gate type field effect transistor (MOS type FET). CONSTITUTION:Row selection signals X1, X2-Xn are selected by a signal ''1'', and column selection signals Y1, Y2-Yn are selected by a signal ''0''. Namely, an n-MOSFET21 in an area applied with the row selection signal ''1'' and the column selection signal ''0'' is read. Therefore, four maximum n-MOSFETs 21 applied with the column selection signal ''0'' at sources turn on and a DC current flows from a power source Vcc through a pull-up p-MOSFET26. The number of n-MOSFET21 in an on state is determined by the number of FETs corresponding to the signals ''0'' and ''1'' stored in the selected column, so the number of FETs 21 in the on state is 0-4 and 2 on average; and current consumption is reduced to <=1/10 and an ROM having a fast operation speed is realized.

Description

DETAILED DESCRIPTION OF THE INVENTION An object of the present invention is to provide an insulated gate field effect transistor (
A read-only memory device that stores information depending on the presence or absence of MO8 type FET.
7, hereinafter abbreviated as ROM), to achieve low power consumption and high-speed operation.

FIG. 1 shows a conventional ROM in which n-MO8 type FMTs 10 for storing information are arranged in a matrix of Xn rows and Ym columns. A row selection signal X1 . X2. . . . Xn is not applied, the drain is connected to the bit lines 11 to 14, and the source is connected to the GND potential. In this case, information in the ROM is accumulated depending on whether or not the drain is connected to the bit line depending on the presence or absence of a contact.

The bit lines 11 to 14 are connected to the power supply VCC by a pull-up n-MO3 whose gate and drain are connected to Vcc.
FET15 is connected, and column selection signal Y1. Y
2. ... n- for column switches with Ym applied to the gate
MO8FET16 is connected. One end of these n-MO5FETs 18 for column switches is the data line 17-
Four types of output signals 0°-03 are obtained from the respective data lines connected to 20 and to which the column selection signal '1' signal is applied to the gate of n→asFET 16. Note that R2 in FIG.
The blocks ˜Rm show how a plurality of the circuit configurations on the left are arranged, and a ROM is configured with this overall arrangement.

In the conventional circuit, row selection signals X1. X2...n-MO3FE for information storage to which '1'' signal is applied among Xn
T10 is turned on, and a DC current flows from the power supply Vaa to GND via the pull-up n~MO3FET15, and the data line becomes 0'' potential.

If there is no MO8FE715, no DC current will flow and the data line will be at a '1' potential. In the case of Figure 1, four columns of FETs 10 are arranged for each column signal, so a maximum of 4Xm FETs can be used. FET1o turns on.

However, since the number of FETs 10 that are turned on is determined by the number of FETs that correspond to the '0'' u 1 ++ multiplied signal stored in the selected column, the number of on-switch FETs 10 is between 0 and 10.
Takes a value between 4Xm. Therefore, on average, 2m FETs 1o are turned on. If the current value flowing from the power supply Vcc to GND via the pull-up n-MO8FET 15 when the FET 10 is turned on is Ic, then the average consumption current of 1 cc is as follows: IcC==2 In X lc Fist*amm ( 1)] is given by.

However, m is the number of column selection signals.

In FIG. 1, there is a drawback that as the number of column selection signals is increased to configure a large capacity ROM, the consumption current Icc increases in proportion to the number of column selection signals. In addition, since the parasitic capacitance 1 of the data line also increases in proportion to the column selection signal, the switching speed of the output signal 0°-03 also becomes slower as the capacity increases. Power consumption, high speed operation RO
It has drawbacks as an M circuit.

It is an object of the present invention to provide a means for realizing a large capacity ROM with lower current consumption and faster operation at the same or higher speed.

FIG. 2 shows a ROM according to an embodiment of the present invention. Information storage n-MO8FETs 21 are arranged in a matrix of Xn rows and Ym rows. A row selection signal x1. x2. . . . Xn is applied and connected to the drain hitt lines 22 to 26.

In this case, information in the ROM is accumulated depending on whether or not the drain is connected to the bit line depending on whether or not a contact window is opened, as in the conventional example. The source of FET21 is supplied with column selection signal Y1. Y2...Ym is applied. bit line 2
2 to 26 have p-MO for pull-up between the power supply Vcc.
8FET2e is connected, and its gate is connected to GND. Bit lines 22-26 are supplied with column selection signals Y1. Y2.
... p-MO for column switch with Ym applied to the gate
5FET27 is connected, and the other end of it is the data line 28.
.about.31, and four types of output signals 0.degree..about.o3 are obtained from the respective data lines. Furthermore, a pull-up p-MO8FET 26' is connected between the data lines 28 to 31 and the power supply VCC as necessary. Furthermore, R2 to Rm in Fig. 2
This block shows a plurality of circuit configurations on the left, and this entire layout constitutes a ROM.

In the case of FIG. 2, row selection signals X1. x2. ...b is selected by the '1" signal, and the column selection signal Y1.Y2...Y
n is selected by the '0' signal. That is, the column selection signal is '0'.
The information storage n-MO8FET 21 in the region to which the 1'' signal and the column selection signal 0'' signal is applied is read out. At this time, the other column selection signals are 1"fti applied, so the information storage n-M (JSFET21 source is at 1" level, so the pull-up p-MO8Fk:
No direct current flows from T26.

Therefore, in the case of Fig. 2, up to four n-MO8FETs 21 whose sources are applied with the column selection signal ``0'' signal are turned on, and a direct current flows from the power supply Vc bow 1 through the pull-up p-MO3FET 26. is lAc9. This turns on n-
The number of MO3FET21 is FET0 corresponding to the +I Q I+, 111n signal stored in that selected column.
Since it is determined by the number, the number of FETs 21 to turn on is 0 to
A value between 4 is taken, and the average is 2. FET2
p-MO for pull-up from power supply Vcc when 1 is turned on
The current value flowing through the 8FET is set to Ic as in the conventional example.
Then, the average consumption current Ice' of the present invention is
is IcC' = 2 x Ic... (
2). In the example shown in Figure 1, as given by equation (1), (
Since it is 2m×Ic, if the present invention is used, the current consumption of the ROM is reduced to 1/m. Moreover, in the case of the present invention,
No matter how large the capacity of the ROM becomes, its sake current is 2I.
c, which is effective for reducing power consumption. For example, considering the case where a ROM is configured at 64 with 8 outputs and 8 outputs, in the 10M configuration shown in Figure 2, n
= 256 and m = 32 can be constructed with two blocks. Therefore, compared to the current consumption in Figure 1, it is 1/32
can be reduced to Furthermore, if Satoshi Otani's 256 has pits or 1M bits, the present invention becomes more effective as the capacity of the ROM increases by 1/64 and 1/1281c, respectively.

FIG. 3 shows another embodiment of the invention. R1, R2...
The block indicated by Rm corresponds to the left circuit block shown in FIG. 1 or 2 and R2...Rm. R1゜R2・
・The block composed of Rm is 2 on the left (l) and right (r).
The row selection signals are common to Xl, X2 . ...Apply the Xn signal. Therefore, the row directions of the left and right blocks are simultaneously selected by the row selection signal. The column selection signal is the block switching signal A, A
are ANDed Yl・A, Y2・A.

(r) and the left block (1). Furthermore, p-mzO8FETs 40 to 47 are connected to the data lines 132 to 39, respectively, as transfer gates for block switching.

The gates of transfer gates 40 to 43 have a signal C,
A signal is applied to the gates of transfer gates 44 to 4γ. Block switching 1K'i When A is "1", the left block is selected, and when A is "1", the right block is selected. At this time, the data line 32 from which output signals 0° to 03 are obtained
．． 36, 33, 37, 34, 38, and 35.39 are divided into two by transfer gates, and the parasitic capacitance of the data line is reduced to about 1/2 compared to the case without transfer gates 40 to 47, and the information Storage n-MO8FET
The discharging time and pull-up time of the bit line and data line by MO8FET 21 are short-circuited, and the charging time of the bit line and data line by MO8FET 26 are short-circuited, thereby enabling high-speed operation of the ROM. In addition, p-MO8FET connected to data lines 32 to 39
48 is a pull-up MOSFET, which has the function of charging the data line in a non-selected state to the "1"level;
Its gate is connected to GND, and its source is connected to the power supply Vcc (g).

In Figure 4, the parasitic capacitance of the data line is reduced to 1/2, similar to Figure 3.
Another embodiment for reducing the

Items with the same numbers as in Figure g3 have the same functions. Common column selection signals for the left and right blocks are Y, , Y2 .・
. . . Apply the Ym signal 9, and apply the AND of the block selection signals A and A to the row selection signal. Therefore, in the case of *f, Figure 4, one column in each of the left and right blocks is selected in the column direction, but only one column in either the right or left block is selected in the row direction.

Therefore, the signal read out to the data line is yj for each column selection.
One block on either the left or right selected by , and in the area where the column selection signal is "0", is read out. In the embodiments shown in FIGS. 3 and 4, their current consumption is the average of the information storage n-MO3FETs in the area selected by one row and one column selection signal, as in the case of FIG. Although the current consumption is proportional to the number (Ice=2Ic in this case),
The parasitic capacitance of the data line is reduced to about 1/2, enabling faster switching operation.

As described in 1- above, by using the present invention, the current consumption is reduced to less than several tenths of that of the conventional method, and the operating speed is high.
M can be realized. In addition, in the explanation of FIGS. 2 to 4, MO8FET 26.26' is used for pull amplifier.

48, MO8FET 27 for column switches, and transfer gates 40 to 47 for block switching are p-MOSFEs.
Although the description has been made using an n-MOSFET, the same function can be achieved using an n-MOSFET.

[Brief explanation of drawings]

FIG. 1 is a conventional ROM circuit diagram, FIGS. 2 and 3. FIG. 4 is a ROM circuit diagram of an embodiment of the present invention. 21---n-MO3FET for information storage, 26.
26'. 48...Pull-up p-MO8FET, 27
"00 row switch p-MO3F ET, 40~
47 ...--- Transfer gate for block switching. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
Figure 'I' + Yz is also Figure 2 Figure 3 No l Figure 4

Claims (1)

[Claims] A row selection signal is applied to the gate of the insulated gate transistor for information storage, the drain is connected to the bit line, and a column selection signal is applied to the source. A read-only memory device comprising: a gate type transistor connected thereto; and a column switch insulated gate type transistor having a column selection signal applied to its gate connected between the bit line and the data line.