JPS58115583A - Video pattern reading system - Google Patents

Abstract

PURPOSE:To obtain a video signal with noise removed, by comparing a signal indicating the boundary peripheral region of a standard pattern with a standard pattern signal for every picture element to discriminate and correct a video pattern signal quickly. CONSTITUTION:The video pattern signal generated by an image pickup device 1 is sent to a binary coded circuit 4, and the output is sent to a binary coded discriminating circuit 7 or the like. The standard pattern signal is stored in a memory 3, and a standard pattern which is made binary under the control of a scan position controlling circuit 2 is detected by the circuit 7. In the boundary peripheral region, the video pattern signal of each picture element is compared with plural picture elements around this picture element. In a region other than the boundary peripheral region, the video pattern signal is compared with the standard pattern signal for every picture element, and the comparison of the picture element of the incoincident video pattern signal is repeated plural times, and a crrected picture element is obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an image pattern reading method suitable for detecting the presence or absence of defects in a pattern of a photomask or the like used in the manufacture of integrated circuits.

Generally, this type of photomask is manufactured using a printing method based on an original drawing (design drawing) (hereinafter referred to as a standard pattern).
For example, it is manufactured by depositing an opaque ROM thin film layer pattern (hereinafter referred to as Eirin pattern) on a transparent glass plate, but it is necessary to inspect whether the pattern is made according to the standard pattern or whether there are any defects. A known inspection method is to use a photographic device including a scanning electron microscope. In this method, the image pattern of the photomask to be inspected is electro-optically read and detected, and the read and detected image signal is binarized for each picture element. After converting the transparent part or white level signal t value to "0"), the video pattern based on this binarized signal is inspected to check for defects. It is necessary to binarize the signal to the correct numerical level, otherwise the accuracy of subsequent inspection will deteriorate and there is a risk of erroneously determining the presence or absence of a defect.

In particular, for video signals with a low S/N ratio, there is a risk that erroneous binarization may be performed due to noise.

Conventionally, in order to solve this problem, in the case of a video signal with a low S/N, the same video pattern is repeatedly scanned and imaged to improve the S/Nt by multiplying the same video pattern by A method is known in which the image pattern is scanned repeatedly over a wide area in this way, so the inspection processing time is extremely long, and it is not uncommon for it to take several days. There were drawbacks.

An object of the present invention is to eliminate the drawbacks of the above-mentioned conventional techniques, quickly remove noise contained in a binarized video signal of a video pattern, and thereby quickly eliminate defects in the video pattern.
This invention relates to a video pattern reading method that enables accurate inspection.

In order to achieve this object, the present invention checks the binarized video signal of the video pattern for each pixel signal, and as a result of the check, pixel signals that may contain noise are checked. Statistical correction is performed by obtaining the pixel signal a plurality of times, and the check is based on the binarized image signal of the standard pattern, and the boundary of the standard pattern [
In the surrounding area including the border (hereinafter referred to as the border surrounding area), the correlation between each picture element of the image pattern is used.
In areas other than the area around the boundary of the standard pattern, the image signals of the standard pattern and the Eirin pattern are compared for each picture element.

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the Eirin pattern reading system according to the present invention, in which 1 is an imaging device, 2 is a scanning position control circuit, 3 is a memory, 4 is a binarization circuit, and 5Fi boundary area A region extraction circuit, 6 a peripheral pixel reference circuit, 7 a binarization condition determination circuit, an 8ViM degree F number circuit, 9 a comparison circuit, and a 1oFiZ value signal setting circuit.

Next, the operation of this embodiment will be explained.

In the figure, an imaging device 1 captures a video turn (not shown) and generates a video signal with a video pattern kW (hereinafter referred to as a video pattern signal). 4, is sampled for each picture element, and is binarized according to the video pattern 01lI!Light.The binarized Eirin pattern signal from the binarization circuit 4 is sampled for each picture element, and is binarized according to the video pattern 01lI!Light. Circuit 6. Binarization condition determination circuit 7
, are supplied to the frequency counting circuit 8.

On the other hand, standard patterns 4 and K of the video patterns imaged by the imaging device 1 are stored in the memory lJ3, and under the control of the scanning position control circuit 2, the video pattern signals are synchronized with the imaging device 1. Similarly, a binarized standard pattern is read out. A video signal representing a standard pattern (hereinafter referred to as a standard pattern signal) is supplied from the memory 3 to a Vi border peripheral area extraction circuit 5. The boundary peripheral area extraction circuit 5 forms a signal representing the boundary peripheral area of the standard pattern (hereinafter referred to as peripheral signal)' from the standard pattern signal, and sends this peripheral signal and the standard pattern signal to the binarization condition determination circuit 7. supply

Note that the "boundary of the standard pattern" refers to the light and shade area of the standard no-turn PS in FIG.
- Okay, [Standard] (Turn boundary surrounding area') is the neighboring area d (shaded area) that includes the boundary Ct of the standard pattern.

Then, when the picture element signal of the standard pattern signal supplied to the boundary peripheral area extraction circuit 5 represents the picture element t'' included in the boundary peripheral area d (FIG. 2) of the standard pattern, the peripheral signal is It is ``0'', and it is 1'' when there is an object represented on a picture element that is not included in the boundary peripheral area d.

The peripheral pixel reference circuit 6 compares each pixel signal of the video pattern signal supplied from the binarization circuit 4 with a plurality of surrounding nine pixel signals that have already been binarized, and calculates each pixel signal. If the signal matches all of the surrounding picture element signals, it is ``l'', and if at least one does not match, a signal (hereinafter referred to as a reference signal) that is 0'' is generated.

That is, in FIG. 813, the picture element signal for the picture element X on the kth scanning line is now supplied to the peripheral picture element reference circuit 6 in the 11th scanning line and the 2nd scanning line of the video pattern. Then, this picture element X, the picture element a+ to the left of picture element 11" of each # element signal with picture element s and d on both sides of element C.
, 'o' levels are compared, and if they all match, the reference signal t'l' is terminated, and if at least one does not match, it is set to %16 //.

The binarization condition judgment circuit 7 judges each pixel signal t of the Eirin pattern signal from the binarization circuit 4 in a different manner according to the peripheral signal from the boundary peripheral area extraction circuit 5.

First, assume that the peripheral signal is 1//.

In this case, the picture elements read from the memory 3 are not included in the vicinity of the boundary *Md shown in FIG. At this time, since the scanning positions of the imaging device Itl and the memory 3 are synchronously controlled by the scanning position control circuit 2, the pixel signals obtained from the imaging device I do not represent the boundaries of the image pattern; The video pattern signal from the binarization circuit 4 and the standard pattern signal from the boundary peripheral area extraction circuit 5 are compared for every t picture element signals. When the two match, the picture element signal of the video pattern signal at that time is supplied to the binary signal setting circuit 10 as a correctly binarized picture element signal, and the scanning position control circuit 2'/ Km made winter imaging device 1
, moves the reading position in memory 3 to the next picture element.

On the other hand, if the two do not match, it is assumed that the pixel signal of the video pattern signal at that time is not correctly binarized, and this may be due to a defect in the video pattern, but it may also be due to noise during reading. This is because there are cases. Therefore, the binarization condition determination circuit 7 operates the frequency counting circuit 8 and fixes the reading position between the imaging device 1 and the memory 3 by the scanning position control circuit 2.

Assume that the next t-highest peripheral signal is 11θ''.

At this time, the picture elements read from the memory 3 are included in the boundary peripheral area d shown in FIG. By the way, in general,
The 6 video patterns read from the imaging device 1 and the standard pattern read from the memory 3 do not completely match, and there is a slight error (41! Based on the quasi-pattern, ±
The error is about 1 μm). For this,
The width of the boundary surrounding class Md in FIG. 2 is lIi quasi-pattern P8
The boundary cf is set at the center of the area with a width of 1 μm in the upper, lower, left, and right directions.
When the video pattern signal is compared with the standard pattern signal by t, even if the pixel signals of each pattern are correct, there is a possibility that the two do not match.

Therefore, based on the reference signal from the peripheral picture element reference circuit 6, each picture element 11 of the video pattern signal from the binarization circuit 4 is
A full judgment is made as to whether No. 1 has been correctly binarized or not.

That is, when reference No. 18 is 411 L/, K is the third
In the figure, the picture element signal corresponding to the picture element xK pair is the surrounding #*
It is assumed that the pixel signals for a + b + c + d match each pixel signal, and from the correlation of the video pattern, the pixel signal for the pixel xK is correctly binarized, and the binarization circuit at this time The pixel signal of the video pattern signal from 4 is supplied to the binary number setting circuit 10, and the scanning position control circuit 2 operates to shift the reading position of the imaging device 1 and memory 3 to the next pixel. .

On the other hand, when the reference signal is Is □ //, K means that in FIG. 3, the pixel signal for pixel X is
BL C! At least one of the pixel signals for ldK differs from the pixel signal, so pixel It is possible that the raw signal was affected.

Therefore, the binary coded condition setting time &87 is the frequency counting circuit 8t-
At the same time, the scanning position control circuit 2t is deactivated to fix the reading positions of the seed taking device 1 and the memory 3.

When activated, the frequency counting circuit 8 starts counting 0" or 1" of the picture element signal of the video pattern signal from the binarization circuit 4. Or, when the scanning is fixed and the same pixel signal is repeatedly sampled in the binarization circuit 4, binarized and input to the frequency counting circuit 8, this binarization level %l 1//
The number of times of binarization (sampling number) that is ``0'' and the number of times that ``0'' is binarized are counted separately, and the number of times (frequency V) of Pa1'' and O''
Which of the number of times (frequency f) is the preset number of times N(
For example, several times), it is detected by the primary comparator circuit 9 whether t- has been exceeded, and if the first one that exceeded 1'0" is "0"t, II I
If N, 111''< is adopted as the true binary number at that reading position, and this is sent to the next stage binary signal setting circuit lO.In this way, the truth or falseness of the binary value is determined depending on the frequency. The reason for this is that the occurrence of noise that causes erroneous signals, subtle temporal changes in the scanning electron beam and the image pattern surface, etc. are only temporary and incidental, and are short-lived compared to correct signal output. This is because it is considered that the frequency is low in terms of time.The comparator circuit 9 immediately operates the scanning position control circuit 2 when it determines that either 110 // or 111 // is kX as described above. Then, the imaging device [1 and the memory 3] start reading the next picture element.

Next, specific examples of each circuit in FIG. 1 will be described. 41N(A) and (13) are block diagrams showing a specific example of the boundary surrounding area extraction circuit 5 in FIG. 1.

In Fig. 4, 11 is the standard pattern Ig input terminal of the memory 3, and 12 is the delay time (corresponding to the horizontal scanning of a television) corresponding to the length of the scanning line.
Shift register 12111221 with IH)...
・”・+ 122n2 t- A group of shift registers connected in series to form a configuration, 13#- each having 2n-4 memory cells, shift register 12□+122.・
..., 12□n-1 and a shift register for serial input and parallel output to which picture element signals are supplied from the input terminal 11 (L'1, P2., ... - pH11) k2
This is a local memory composed of n -1 memory. With this configuration, a square local area consisting of a standard pattern having a number of picture elements of (2n-1) x (2n-1) in length and width is successively cut out in the local memory 13 in synchronization with scanning.

For example, if n=3, (2n 1)
2n-1) A square area consisting of -5X5=25 picture elements is extracted according to the scanning position, and if the width of one picture element to is 2 μm, this square region has a width tl of 1 μm.
X1 μm.

In Fig. 4 03), 14FiAND circuit, 15 is N
OR circuit 16 is an OR circuit. All pixel signals tAND circuit 14 stored in local memory I713K as memory cells tPij (j=1 to 2n-1) of local memory 13
is input to the NOR circuit 15, and the output of the AND circuit 14 and the NOR circuit 15 is input to the OR circuit 16.
The peripheral signal obtained at the output terminal 17 of the R circuit 16 is tt 1 // when all the picture elements in the local memory 13 match, and is 11 when even one of them is different.
0".

Therefore, the operation of the boundary surrounding area extraction circuit 5 will now be explained with reference to FIG. 5 using an example of n-=2.

In Fig. 5, a is the boundary of the standard pattern, and the circle mark is the boundary of the shift register of the local memory 13 (Fig. 4 (A)). The picture element corresponding to the stored picture element signal is shown in the shift register (7) to simplify the explanation.
It is expressed as picture element tPB stored in j.

Now, as shown in Figure 5, all picture elements Plj are on the boundary a.
When it is on one side of , all the picture elements P1j match, so the peripheral signal obtained at the output terminal 17 (in FIG. 4) is 111".

Next, the reading position of the memory 3 (Figure 1) moves to the right by one picture element, and as shown in Figure 5 (can), it is on the right side of the picture element Piz-da boundary a, and picture element Pia are boundary a
When it is on the left side of , the picture element pH and the picture element Piz +
Although obviously different from Pim, the peripheral signal from the output terminal 17 is 1'0''.

Furthermore, the memory 3 moves the reading position, and as shown in FIG.
As shown in , picture element P11+Pig is on the right side of boundary a, and 11! When the bulk P1g becomes the left @ of the boundary a,
The peripheral signal from the output terminal 17 turns ON, but if the reading position moves, all picture elements Plj will be on the right side of the boundary 1, and the peripheral signal Fi411 from the output terminal 17 will turn on. (Figure 5, 0).

From the above, since the peripheral signal from the output terminal 17 becomes "0" with a width of two picture elements, the width l of the boundary peripheral area for one boundary a is 2 as shown in FIG. 5(E). Picture element -1
-1 picture element. Generally, the picture element Pi to be memorized
If the number t of j is (2n-1)X(2n-1), it corresponds to the width of the boundary surrounding area for the boundary aK/Fi(n-1) picture elements.

Although FIG. 6 describes the case where the pattern boundary 1 is in the vertical direction, the same applies to the case where the pattern boundary is in the horizontal direction, and the number of picture elements pij to be stored is (2n- 1) When X (2n-1), it is possible to form a border peripheral region with a width of ±(n -1) picture elements with respect to the border.

Next, local memory 130 each shift register (Fig. 4 (A)
The relationship between the picture element P stored in )) and the picture element of the video pattern read by the imaging device I will be explained.

Now, as explained in FIG. 5, it is assumed that n=2 and the local memory 13 (FIG. 4(A)) is composed of three shift registers each having three memory cells.

In this case, as explained in FIG. 5, the allowable deviation amount of the video pattern from the standard pattern is ±l, that is,
It is ±1 picture element. That is, in FIG. 5, with respect to the boundary a of the standard pattern, the corresponding boundary of the video pattern is allowed to deviate from bl to t by l picture elements on the left and right of the boundary a.

Therefore, when the picture element Plj is stored in the shift register of the local memory 13 as shown in FIG. ) must be on the left side of the boundary of the Eirin pattern (hereinafter referred to as boundary) that corresponds to boundary a of the standard pattern.

However, the picture element Pij stored in the shift register is the fifth
When the picture element of the video pattern to be read becomes as shown in Figure (E), it is unclear which of the boundaries (illK A) the corresponding picture element of the image pattern to be read is. When it is a divided bl, the current axillary picture element is the boundary b
It must be on the right side of 8.

Next, even if the picture element P1j stored in the shift register becomes as shown in FIG. 5(C), it is still unclear which side of the boundary the picture element is on. When the boundary is shifted one picture element to the left to the boundary b1, the picture element is on the right side of the boundary, but when it is shifted to the right to the boundary b1, the picture element is on the left side of the boundary. .

Further, K, the picture element Plj stored in the shift register is the fifth
When K is reached as shown in Figure (D), the picture element must be on the right side of the boundary.

From the above, picture element P1 stored in local memory 13
j, P□, P1. and one of the statues fjtt (first
In order to compare each pixel signal of the video pattern signal from FIG. 1, the pixels of the standard pattern being read from the memory 3 (FIG. 1) must be identical. Similarly, if we consider the case where the boundary & (FIG. 5) is in the horizontal direction, the picture elements pat, pg□.

One of Pa11 and the picture element of the standard pattern being read from the memory 3 must be the same. Therefore, the picture element psi and the picture element of the standard pattern being read must be the same.

Generally, the local memory 3 is (2n-1)X(2n-1)
If one picture element is to be stored, the picture element stored in Pnn must be the same as the picture element of the standard pattern being read. ') Then, the pixel signals for the standard pattern pixels read from the memory 3 (Fig. 1) in synchronization with the picture elements of the image turn read by the imaging device 1 (Fig. 1) are as follows: It will be stored in the storage cell Pnn of the shift register of the local memory IJ13 (FIG. 4(A)) of the boundary surrounding area extraction circuit 5.

Since the boundary surrounding area extraction circuit 5 operates in this way,
In FIG. 1, from the memory 3, in addition to the standard pattern signal for comparison with the video pattern signal from the conversion circuit 4, a standard pattern signal that is earlier than the turn signal in time is transmitted around the boundary. Input terminal 1 of region extraction circuit 6
1 (wJA diagram GA)).

Therefore, we are now looking at the maximum possible amount of distortion of the video pattern relative to the standard pattern! (Fig. 5) is 111 m, and
If the distance between each picture element to is 2 μm, a shift of 5 picture elements must be allowed. Therefore, since n-1=5,', n=6, 2n-1=11, and the shift register group 12 in FIG. 4(A)
is a shift register 111 with 10 (=2×6-2) cascade-connected shift registers 1 and 11 stages of local memory 13Fi.
(1), the same pixel signal as the pixel signal stored in the memory cell P, , of the shift register may be read from the memory 3 in synchronization with the pixel signal read from the camera l.

FIG. 6 is a block diagram showing an embodiment of the peripheral picture element reference circuit 5 shown in FIG. In FIG. 6, it is an input terminal for the video pattern signal from the 18Fi binarization circuit 4, and 19
20 is a shift register with one column input and parallel output, and 21 is an ExOR circuit. # (exclusive OR circuit), 22 is a NOR circuit.

In this example, the shift register 2o has five storage cells al
b+ el a, xk, and for the input picture element from the input terminal 18, as shown in FIG. I remember the basics. The pixels stored in the memory cell X from the input terminal 18 are the surrounding four pixels a −
Only when all of d match, the signal at the output terminal 23 becomes "11", otherwise it becomes st Ott.

FIG. 7 is a block diagram showing an embodiment of the binarization condition determination circuit 7 in FIG. #'i is an AND circuit, 32.33 is an inverter, 34.35 is an OR circuit, 36.37 is an OR circuit, 38 is a gate circuit, and 39, 40, and 41 are output terminals.

Next, the operation shown in FIG. 7 will be explained.

In the same figure, the input terminal 24 is connected to the FiZ value conversion circuit 4 (first
The input terminal 25 is supplied with Eirin pattern notes from (Fig.).
A standard pattern signal from the boundary surrounding area extraction circuit 5 (Fig. 1) is supplied to the input terminal 26, and a peripheral signal from the output terminal 17 (Fig. 5) of the boundary surrounding area extraction (b) circuit 5 is supplied to the input terminal 26. Furthermore, a reference signal from the peripheral picture element reference circuit 6 (FIG. 1) is supplied to the input terminal 27.

First, when the peripheral signal from the input terminal 26 is "l", that is, the picture element of the standard pattern read by the memory 3 (FIG. 1) is in an area other than the boundary area d (FIG. 2). If 1!Kii, one input terminal of the AND circuits 30 and 31 becomes ``11'', and the AND circuits 34 and 35tl inverter 32 causes the output ff1-jt to have a level Fi ``0''.

On the other hand, the video pattern signal from the input terminal 24 is supplied to the ExOR circuit 28 together with the gate circuit 38, and is compared with the standard pattern I from the input terminal 25 for each cell element. OII.

If they do not match, an output of 11'' (No. 1 is generated).

When the output signal of the ExOR circuit 28 is 10'', AN
The level of the output signal of the D circuit 31 is "0", and as a result, the signal obtained at the output terminal 41 via the OR circuit 37 is "0".

On the other hand, the 11O" output signal of the EXOR circuit 28 is inverted by the inverter 29 and becomes 1", and the AND circuit 3
0 is turned on and the signal "l" is supplied to the gate circuit 38 and the output terminal 40 via the kOR circuit 36.For this reason,
The gate circuit 38 is turned on and supplies the picture elements of the video pattern matching the standard pattern to the output terminal 39.

When the output g@ of the ExOR circuit 28 is 1", the AN
D circuit 30! The signal 111 // is supplied to the output terminal 41 via the OR circuit 37 since the AND circuit 31 is turned on and does not generate the signal ``1''. On the other hand, since 30.34 AND circuits are off,
The gate circuit 38 is closed, and the output terminal 40 is connected to Sl.
The faith of “g” is provided.

Next, the peripheral signal from the input terminal 26 is 0'', that is,
AND
When the circuits 30 and 31Fi are off, one input terminal of the AND circuit 34 and 35 is 11'' due to the inverter 32.

Therefore, reference No. 11 from input terminal 27 is 4% I L
/, AND circuit 34 tri turns on, AND
Circuit 35H is turned off. A 1'' signal from the AND circuit 34 is supplied to the gate circuit 38 and the output terminal 40 via the OR circuit 36t, and the gate circuit 38 (L- is opened to output the picture element of the video pattern No. 16 from the input terminal 24 at that time). It is supplied to the output terminal 39.

On the other hand, when the input signal from the input terminal 27 is "0", the AND circuit 34 is turned off, and the AND circuit 35 is turned on by the inverter 33. vll from the AND circuit 35
The signal is supplied to the output terminal 41 via the OR circuit 3711-.

Note that the signal at the output terminal 29 is output from the binary signal setting circuit 10 (
1), the signal at the output terminal 40 is supplied to the scanning position control circuit 2, the signal at the output terminal 41 is supplied to the frequency stitch count circuit 8, and when the signal at the output terminal 40 is "1", The scanning position control circuit 2 operates to move the image pickup device 1 and the pattern reading position t1 of the memory 3 by the pixel.

FIG. 8 is a block diagram showing an embodiment of the frequency counting circuit 8 and the comparison circuit 9 shown in FIG. 1, in which 42 is an input terminal;
3 is an inverter, 44.45t'i each counter, 46
．． 47 are comparison circuits, 48° and 49 are input terminals, 5
0 is a selection circuit, 51 is an OR circuit, and 52 and 53 are output terminals.

Next, the operation shown in FIG. 1 will be explained.

In the figure, the output terminal 41 of the binarization condition determination circuit 7
When the signal shown in FIG. 7 becomes II 1 //, the counters 44 and 45 are activated. At this time, as mentioned earlier, since the output signal of the output terminal 40 of the binarization condition determination circuit 7 is 110", the scanning position control circuit 2 becomes inactive, and the imaging device 1 and the memory 3 ( (Figure 1) The reading position t of the pattern based on K is fixed, and the input terminal 42 supplies a pixel signal for the same pixel of Eirin < turn.

The counter 44 then receives the "l" value appearing at the input terminal 42).
The number of occurrences of " is counted, and the counter 45 is the inverter 43
Therefore, the number of occurrences of 0" is counted. The voltage that changes according to this number of times is the reference voltage from the input terminal 48.49 corresponding to the number N preset by the comparator 46.47, respectively. They are compared, and when one of them matches the reference voltage, an output signal is output, and this output signal selects either one of the selection circuit 50tf%%t" or "O" and outputs it to the output terminal 52 as a binary signal. Output.

The output signals of the comparison circuits 46 and 47 are also supplied to the OR circuit 51, and are sent to the scanning position control circuit 2 (first
image capture device 1 and memory 3 (Figure 1111).
The pattern reading position fk is moved to the next picture element.

By the way, as shown above, the counters 44 and 45 display 177. of the same picture element. The reason for counting %IO is because, as mentioned earlier, even if the video pattern signal contains noise, this noise is not fixed but changes from moment to moment. When the same pixel is read repeatedly, the frequency with which the pixel signal is not affected by noise is generally greater than the frequency with which it is affected by noise, so the frequency with which the pixel signal is not affected by noise is generally greater than the frequency with which the pixel signal is affected by noise. A counter with a pixel signal that is not affected by this will reach the set value N faster, and it may be statistically determined that the input signal of the counter that reaches the set value N faster is the correct one. This is due to being deaf.

For example, suppose that the picture elements to be compared between the standard pattern and the video pattern are l Q // and 111 N, respectively, and the books do not match, and the picture element of the video pattern at that time is actually 1tO ”.

Therefore, by repeatedly reading the pixel signal for the pixel of this video pattern and supplying it to the t counter 44.45, the frequency at which the pixel signal of It O// is supplied becomes ``1''.
Since it is statistically more frequent than the frequency at which pixel signals are supplied,
The count number of the counter 45 reaches the set value N more quickly,
An output is generated from the comparison circuit 47 and output from the selection circuit 50 to 1'.
A pixel signal of 0" is obtained. There is no major error even if this pixel signal of 1"0 is regarded as a correct pixel signal.

FIG. 9 is a block diagram showing a specific example of the binary signal setting circuit 10 of FIG. 1, in which 54 is a selection circuit, 55, 56 .
57 and 58 are input terminals, and 59 is an output terminal.

Next, the operation shown in FIG. 9 will be explained.

In the figure, signals from output terminals 39 and 40 (FIG. 7) of the binarization condition determination circuit 7 are supplied to input terminals 55 and 57, respectively. Comparison circuits 9 are connected to input terminals 56 and 58, respectively.
A signal is supplied from the output terminals 52, 53 (FIG. 8) of the.

That is, each pixel signal of the video pattern signal from the tiZ value conversion condition determination circuit 7 is supplied to the input terminal 55, and the pixel signal of the video pattern signal from the comparison circuit 9 is supplied to the input terminal 56, respectively.

Then, the selection circuit 54 selects a pixel signal from one of the input terminals 55 and 56 according to the signal supplied from the input terminals 57 and 58, and a video pattern signal containing no noise is obtained at the output terminal 59. It will be done.

In this way, it is possible to generate a video pattern signal that can accurately inspect defects in the video pattern.
It is clear that the embodiments of the circuits of FIG. 1 shown so far are merely examples, and that other circuits having equivalent functionality may also be used.

Furthermore, as explained in FIG. 5, the boundary surrounding area d in FIG. This can be set arbitrarily depending on the direction in which the leech deviation occurs.

As explained above, misfire f! According to AK, a video pattern formed based on a standard pattern is removed, and the resulting video pattern signal is determined and corrected for each pixel signal, and the determination of each pixel signal is as follows: The border surrounding area is set by taking into account the reading and time difference between the standard pattern and the video pattern, and when each pixel signal represents a pixel outside the border surrounding area, each pixel signal and the standard for the standard pattern are set. This is done by comparing each pixel signal of the pattern signal, and when each pixel number of the video pattern signal represents a pixel 'Jk in the peripheral area of the boundary, the correlation of the video pattern is used. Furthermore, for pixel signals that may contain noise according to the above judgment, the frequency distribution of 1'1' and 0' of the pixel signal obtained by repeatedly reading the picture elements of the video pattern is determined. Since each pixel signal is corrected using
Even if there is a discrepancy between the video pattern and the standard pattern, it does not take a particularly long time and is accurate.
Therefore, defects in the image pattern can be quickly and accurately inspected, and an image pattern reading method with excellent functions can be provided without the drawbacks of the prior art.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the video pattern reading method according to the present invention, FIG. 2 is an explanatory diagram showing the boundary peripheral area of the 1-1m quasi-pattern, and FIG. 3 is the peripheral pixel reference circuit of FIG. 1. Figure 4 (A), (
B) Ti A block diagram showing a part of an embodiment of the boundary surrounding area extraction circuit in FIG. 1, FIG. 5 (A), (B),
(C), (D), and (E) are explanatory diagrams showing the operation of FIG. 4, FIG. 6 is a block diagram showing an example of the peripheral pixel reference circuit of FIG. 1, and FIG. FIG. 8 is a block diagram showing an embodiment of the binarization condition determination circuit shown in FIG.
FIG. 9 is a block diagram showing an embodiment of the binary signal setting circuit of FIG. 1. 1... Imaging device, 2... Scanning position control circuit, 3... Memory, 4... Binarization circuit, 5... Boundary surrounding area extraction circuit, 6...
... Peripheral pixel reference circuit, 7 ... Binarization condition judgment circuit, 8 ... Frequency counting circuit, 9 ... Comparison circuit, 10 ... Binary signal setting circuit. Agent Patent Attorney Takeshi Kenjibe (and 11 others) Figure 2 Name 3 Figure 4 (A) (B) Figure 5 Figure 6 Figure 11 Ji 8 Figure 5 I -, C 9 1:;-, 1 75B Continuing from page 1 (n) Inventor: Hitachi, Ltd., Hitachi, Ltd. Production Technology Laboratory, 292 Yoshida-cho, Totsuka-ku, Yokohama 2) Inventor: Nobuhiko Aoki, Hitachi, Ltd., Production Technology Laboratory, 292 Yoshida-cho, Totsuka-ku, Yokohama

Claims (1)

[Claims] A binarized video pattern signal is obtained by photographing a video pattern formed based on a standard pattern, and defects in the video pattern can be detected using the video pattern signal. In the second method of reading the video pattern, a standard pattern signal is obtained from the standard pattern in synchronization with the video pattern signal, a region around the boundary between the standard pattern and the pattern is detected using the standard pattern signal, and a region around the boundary between the standard and the pattern is detected. In the peripheral area, the Eirin pattern signal is compared for each picture element with the skeleton picture element and a plurality of picture elements surrounding the picture element,
In a region other than the border peripheral region, the Eirin pattern signal and the standard pattern signal are compared for each pixel, and if the video does not match as a result of the respective comparisons (the pixel of the turn signal is repeated several times) A corrected pixel is obtained by obtaining the corrected pixel, and the video pattern signal, which is composed of nine pixels of the video pattern signal that match the corrected pixel by the respective comparisons, and from which noise has been removed is obtained. Eirin pattern reading method is characterized by being configured so that it can be read.