JPS58115550A - Interrupt processing system - Google Patents

Abstract

PURPOSE:To read plural interruptions which are close in respect to time, by giving the assembling processing function to an I/O control program, and giving the decomposing processing function to an asynchronous exit program in the device control system. CONSTITUTION:The assembling processing function is given to the I/O control program of a device control processor 2, and the decomposing processing function is given to an asynchronous exit program 11. Plural attention information 2' and 3' which are raised closely in respect to time are collected as one transfer data on a transfer buffer 8, and a transfer request is issued. When transfer data is received by a host processor 3, respective attention information are decomposed and are queued in an attention queue 16.

Description

[Detailed Description of the Invention] 4. Technical Field of the Invention The present invention relates to an interrupt processing method, particularly for example, a graphic processing method.
In a data processing system having a display, etc., the display control processor is configured to notify the host processor of multiple AtenV errors from the graphics display, thereby reducing the number of interrupts to the host processor. (C) Background of the Technology The present invention is applicable to, but is not limited to, a data processing system having a graphic Φ display.
; in the applicant's company, the display is controlled by a relatively small processor called the U series, and the U series processor interrupts the Azone VW from the display to the large processor also called the MV series. It is designed to notify you by emitting a message.

Conventionally, in the above-mentioned V stem, even if a plurality of Azone V1 units are raised relatively close to each other in time from the display side, the U series processor (herein referred to as a device control processor or display control processor) For each attention, the M series processor (herein referred to as host
(sometimes referred to as a processor). In other words, when three Azone V-seals were raised, five interrupts were issued.

This can undesirably increase the load on the host processor as the display is used more frequently.

(q Object and Structure of the Invention The present invention aims to solve the above points. 1) The interrupt processing method of the present invention includes an input/output device, a device control processor that controls display for the input/output device, and a device control processor that controls the display for the input/output device. A host processor for communicating with the processor is provided, and in response to an interrupt from the device, the device control unit generates an interrupt to the host processor and sends interrupt information to the small processor. In the device control system configured to read the information, the device control processor reads the information at the stage when an interrupt information queue and a line side information queue for queuing each side information in response to an interrupt from the device are formed. An I10 management program that issues a transfer request to the host processor side and processes the above-mentioned interrupt information in multiple pieces, and processes the contents of the above-mentioned interrupt information queue and each side interrupt information or each of the above-mentioned multiple pieces of interrupt information in one piece. It has at least a transfer buffer for storing data as one unit.

The host processor is a processing program that reads each unit of transfer data in response to an interrupt from the device control processor, and performs a process of disassembling the unit into each side input information.

Input 1 < Sofa, where each unit of the above transfer data is stored; an interrupt information queue in which each unit on the input buffer is stored in a disassembled form for each interrupt information; the contents of the interrupt information queue are stored one by one; A supervisor program that extracts and supplies the interrupt information to the user program, and at least a user program that uses the supplied interrupt information are provided, and the number of pieces of interrupt information recorded in the unit of transfer data is described. It is characterized by This will be explained below with reference to the drawings.

0 Embodiment of the Invention FIG. 1 shows an embodiment of a device control system to which the present invention is applied, and FIG. 2 shows the configuration of an embodiment of the interrupt processing system of the present invention.

In FIG. 1, 1 represents a DisGray, 2 represents a DisGray control processor, and 3 represents a host processor. The display gray control processor 2 controls the display gray, and when an attention message is issued from the display 1, it holds attention information corresponding to the attention message and sends it to the host.
An interrupt is issued to the processor 3 to cause the host processor 3 to read the above attention information.

Generally, the configuration is as described above, but conventionally, as described in the "Technical Background and Problems" section above, an interrupt has been issued to the host processor 5 for each attention.

FIG. 2 shows the configuration of an embodiment that solves the above problems. Reference numerals 1 and 2.5 in the figure correspond to those in FIG. And 4 is the interrupt output program (sha 1),
Each attention from the display ■, ■, ■...
It works by queuing... to create an attention cue 7. Reference numeral 5 denotes an I10 management program which, when activated from a waiting state, prepares the contents of the attention queue 7 in a transfer buffer 8 and requests the host processor 3 to transfer the contents.

That is, an interrupt is performed. However, in the present invention, the I1
0: W Coral Program 5 has an "assembly" process prepared for multiple items (3 or more 4 pieces) that are placed close together within 2 hours.
The attention information (acceptable) is collected as one transfer data on the transfer buffer as shown in the figure (2) and (2), and the above-mentioned transfer request is made. 6 is the interrupt output lob program (+
2), when desired transfer data is received by the host processor 3 in response to one interrupt, the transfer buffer is released and the I10 management program 5 is notified of this fact.

Reference numeral 7 represents the above-mentioned attention queue, and reference numeral 8 represents a transfer buffer that is prepared for a plurality of pieces of information.If necessary, a plurality of pieces of attention information may be stored together as one, as shown in the figure. be.

9 is an attention handler, and 10 is an activity, each of which performs processing corresponding to the above-mentioned interrupt. 1
Reference numeral 1 denotes an asynchronous output lob program (valve 1), which reads transfer data into the input buffer 15 using the BXCP macro in response to the above-mentioned interrupt, and loads the data into the attention queue 1.
It performs the function of queuing to 6. However, in the case of the present invention, when a plurality of pieces of attention information are grouped together in the contents of one input buffer 15 as shown in the figure (■) and (■), a "disassembly" process is prepared.
Each piece of attention information is decomposed and queued in the attention queue 16.

12 is an asynchronous output lob program (+2).

When the program starts working, it generally waits (wA i
T) functions to start the user program 13 in the state. 13 is a user program.

Started by the above asynchronous output roderogram (+2),
The supervisor call program 14 is requested by the supervisor call yv (8V C) command to receive one attention information on the attention queue 16. 14 is.

It is a supervisor program and functions to deliver the contents of the attention queue to the user program 13. Further, 15 represents an input puffer, 16 an attention queue, and 17 a user area.

In the case of the present invention, the above-mentioned I10 management program 5 is provided with an "L assembly" processing function.

A major feature of the above-mentioned non-interrogative Roderoghum (+1) 11 is that it has a "disassembly" processing function. The transfer data collected in the transfer buffer 8 is formatted, for example, in the format of the transfer data 18J as shown in the lower center of FIG. That is, -・
The node section has (1) the total length of attention VWI and (11) the number of attentions, and the data section is configured so that a plurality of pieces of attention information can be prepared.

In the case of the embodiment, the range in which multiple pieces of attention information are combined into one is the range that occurs during preparation for causing an interrupt on the host side, and is read by Ilo from the host side as necessary. The latency information up to that point may be summarized.

(g)) As described in detail, according to the present invention, it is possible to combine multiple interrupts issued close to each other in one hour into one and have the host processor read it. Become. This makes it possible to reduce the amount of processing load on the host processor accordingly.

[Brief explanation of the drawing]

FIG. 1 shows an embodiment of a device control system to which the present invention is applied, and FIG. 2 shows a configuration of an embodiment of the interrupt processing method of the present invention. In the figure, 1 is the display, 2 is the device control unit,
3 is a high-speed processor, 4 is an interrupt output program, 5 is an I10 management program, 7 is an attention queue, s is a transfer program, 11 is an asynchronous output program (ll), 13 is a user program, 14 is Supervisor Call Groft 151d Input t<Sofa, 16 is Attention Queue, 17 is User Territory,
18 represents transfer data. Patent applicant Hiroshi Mori (1 other person), agent patent attorney of Fujitsu Ltd.

Claims (1)

[Claims] The device control processor includes a device control processor that controls an input/output device, a display for the input/output device, and a host processor that communicates with the device control processor, and in response to an interrupt from the device, the device control processor controls the host processor. In a device control system configured to generate an interrupt to a device and cause the host processor to read interrupt information, the device control processor queues each interrupt information in response to an interrupt from the device. An I10 management program that issues a transfer request to the host processor at the stage when an interrupt information queue and a chain side interrupt information queue are formed, and also performs processing to collect multiple pieces of the interrupt information, and the contents of the interrupt information queue and each 1 for each interrupt information or for each of the above multiple pieces of interrupt information
The host processor reads each unit of transfer data in response to an interrupt from the device control processor side, and decomposes the unit into each interrupt information. an input buffer in which each unit of the transfer data is stored; an interrupt information queue in which each unit on the input buffer is stored in a form in which the interrupt information is disassembled; and the interrupt information queue. At least a supervisor program that extracts the contents one by one and supplies them to the user program, a user program that uses the supplied interrupt information, and a supervisor program that extracts the contents one by one and supplies them to the user program, and a user program that uses the supplied interrupt information. An interrupt processing method characterized by the number of interrupts being described.