JPH033063U

JPH033063U -

Info

Publication number: JPH033063U
Application number: JP6224589U
Authority: JP
Priority date: 1989-05-29
Filing date: 1989-05-29
Publication date: 1991-01-14

Description

[Brief explanation of drawings]

第１図は本考案に係る座標変換処理装置の第１
の実施例のブロツク図、第２図はマトリツクスパ
ラメータフアイルの構成例を示す図、第３図は第
１図に示す座標変換処理装置の処理流れを示すフ
ローチヤート、第４図は第１図の座標変換処理装
置で実行される座標変換処理の一例を示す図、第
５図は本考案に係る座標変換処理の第２の実施例
のブロツク図、第６図はセレクタのトグル的な選
択による入力データレジスタ、出力データレジス
タ、マトリツクスパラメータテーブルの動作を示
す図、第７図は第５図の座標変換処理装置の処理
流れを示すフローチヤート、第８図ａ，ｂは第５
図の座標変換処理装置における主プロセツサ、コ
プロセツサの動作をそれぞれ示すタイムチヤート
、第９図ａ，ｂは第８図ａ，ｂとの比較のために
従来の座標変換処理装置における主プロセツサ、
コプロセツサの動作をそれぞれ示すタイムチヤー
ト、第１０図は本考案に係る座標変換処理装置の
第３の実施例のブロツク図、第１１図、第１２図
は第１０図のデータ入力用ＦＩＦＯ部、データ出
力用ＦＩＦＯ部の具体例をそれぞれ示す図、第１
３図は第１０図のマトリツクス演算器の具体例を
示す図、第１４図は累積器の一例を示す図、第１
５図は従来の一般的な座標変換処理装置のブロツ
ク図、第１６図は従来のコプロセツサのブロツク
図、第１７図は座標変換処理の一例を示す図、第
１８図は従来の座標変換処理装置の処理流れを示
すフローチヤートである。１，１０，４０……コプロセツサ、２……レジ
スタ群、３……コマンド／パラメータアドレスレ
ジスタ、４，２１……ステイタスレジスタ、５，
２２，２３……入力データレジスタ、７……マト
リツクスパラメータフアイル、２０……コマンド
レジスタ、２６，２７，１０６……出力データレ
ジスタ、３０，３１……マトリツクスパラメータ
テーブル、２４，２５，２８，２９，３２，３３
……セレクタ、３５……セレクタコントローラ、
３６……マイクロプログラムドマトリツクス演算
器、４１……データ入力用ＦＩＦＯ部、４３……
データ出力用ＦＩＦＯ部、４７……インタラプト
コントローラ、９０，９１，９２……主プロセツ
サ。 FIG. 1 shows the first coordinate transformation processing device according to the present invention.
2 is a diagram showing an example of the configuration of a matrix parameter file, FIG. 3 is a flowchart showing the processing flow of the coordinate transformation processing device shown in FIG. 1, and FIG. 4 is a diagram showing an example of the configuration of a matrix parameter file. 5 is a block diagram of a second embodiment of the coordinate transformation processing according to the present invention, and FIG. 6 is a diagram showing an example of the coordinate transformation processing executed by the coordinate transformation processing device of FIG. 7 is a flowchart showing the processing flow of the coordinate transformation processing device of FIG. 5. FIGS.
A time chart showing the operations of the main processor and coprocessor in the coordinate transformation processing device shown in the figure, respectively. FIGS. 9a and 9b show the main processor in the conventional coordinate transformation processing device for comparison with FIGS.
FIG. 10 is a block diagram of the third embodiment of the coordinate transformation processing device according to the present invention. FIGS. 11 and 12 are time charts showing the operation of the coprocessor, and FIG. Figures showing specific examples of the output FIFO section, Part 1
3 is a diagram showing a specific example of the matrix calculator in FIG. 10, FIG. 14 is a diagram showing an example of the accumulator,
FIG. 5 is a block diagram of a conventional general coordinate transformation processing device, FIG. 16 is a block diagram of a conventional coprocessor, FIG. 17 is a diagram showing an example of coordinate transformation processing, and FIG. 18 is a conventional coordinate transformation processing device. This is a flowchart showing the processing flow. 1, 10, 40... Coprocessor, 2... Register group, 3... Command/parameter address register, 4, 21... Status register, 5,
22, 23... Input data register, 7... Matrix parameter file, 20... Command register, 26, 27, 106... Output data register, 30, 31... Matrix parameter table, 24, 25, 28, 29, 32, 33
...Selector, 35...Selector controller,
36...Microprogrammed matrix computing unit, 41...FIFO section for data input, 43...
FIFO section for data output, 47...interrupt controller, 90, 91, 92...main processor.

Claims

[Claims for Utility Model Registration] 1. A main processor and a coprocessor that performs coordinate transformation processing on source coordinate data from the main processor using matrix parameters and outputs destination coordinate data as a calculation result, the coprocessor comprising: A matrix parameter storage means capable of storing a plurality of matrix parameters, and an address storage means for storing the address of the matrix parameter used in the coordinate transformation calculation from the main processor. 1. A coordinate transformation processing device, characterized in that it is pointed by an address stored in address storage means. 2. It has a main processor and a coprocessor that performs coordinate transformation processing on source coordinate data from the main processor using matrix parameters and outputs destination coordinate data as a calculation result, and the coprocessor stores a plurality of source coordinate data. a plurality of input data storage means for storing a plurality of matrix parameters; a plurality of output data storage means for storing a plurality of destination coordinate data; togglingly selecting a plurality of input data storage means; togglingly selecting the plurality of matrix parameter storage means;
A coordinate transformation processing device comprising: a selection means for toggle-like selection of the plurality of output data storage means; and a selection control means for controlling the toggle-like selection of the selection means. 3. A main processor, and a coprocessor that performs coordinate transformation processing on source coordinate data from the main processor using matrix parameters and outputs destination coordinate data as a calculation result, and the coprocessor has matrix calculation means for performing calculations. , an input data buffer means in which source coordinate data and matrix parameters from the main processor are sequentially stored as an input data set, and input data buffer means for sequentially supplying the stored data set to the matrix calculation means; and destination coordinate data from the matrix calculation means. output data buffer means for sequentially storing data as an output data set and sequentially supplying the stored data set to the main processor; and notification means for notifying the matrix calculation means of the states of the input data buffer means and the output data buffer means. A coordinate transformation processing device comprising: