JPS58114510A - Power amplifier - Google Patents

Abstract

PURPOSE:To reduce the distortion factor and to expand the dynamic range, by providing a bias control means and a power supply voltage control means and controlling the bias and the power supply voltage of a power amplifier means together based on the signal to be amplified. CONSTITUTION:A signal level detection circuit 9 outputs detected signals to a bias control circuit 10 and a power supply voltage control circuit 11. When a signal level is low, the circuit 10 controls a bias circuit 4 so as to bias transistors (TRs)1a, 1b to class A(or AB). The circuit sets off switch circuits 8a, 8b to decrease the power supply voltage. Further, when the signal level is high, the circuit 10 controls the circuit 4 so as to bias the TRs 1a, 1b to class B. Simultaneously, the circuit 11 closes the circuits 8a, 8b and increases the power supply voltage.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a power amplifier that has both a low distortion factor of 2 when amplifying small signals and high efficiency when amplifying large signals.

A class A amplifier has the advantage of having an extremely low distortion factor, so if it is used as an audio amplifier, extremely good sound quality can be obtained. However, due to its operating principle, class A amplifiers have the disadvantage of extremely low power efficiency, which makes it difficult to convert them into output.

Conventionally, as a power amplifier that takes advantage of the above-mentioned advantages of a class-A amplifier and overcomes the above-mentioned drawbacks, there is a known power amplifier in which input operation and class-B operation can be selected by switching a manual switch. It is being That is, in this power amplifier, when the manual switch is set to one of the switching positions, the bias sweetness of the power amplification stage is increased, class A operation is selected, and the power supply voltage supplied to the power amplification stage is decreased. On the other hand, when the manual switch is set to the other switching position, the bias voltage is decreased and class B operation is selected, and the supply voltage is increased to increase the power. It was made so that it could be obtained. However, in such a power amplifier, when class A operation is selected, the power supply voltage is lowered as described above, so that only a signal with a lower maximum signal level can be amplified than when class B operation is selected. There were 9 problems in which the dynamic range became narrower (that is, the dynamic range became narrower).

On the other hand, in recent years, digitalization of audio amplifiers has become commonplace, and there is a strong desire to realize a power amplifier that can achieve both low distortion and a wide dynamic range.

In view of the above circumstances, the present invention was made with the purpose of providing a power amplifier that can efficiently amplify large signals while ensuring a low distortion rate for small signals. Based on this, when the signal level is low, the bias amount of the power amplification stage is increased to reduce distortion, and the power supply voltage is decreased to reduce loss.
On the other hand, when the signal level is high, the bias amount of the power amplification stage is reduced and the power supply voltage is increased, so that efficient amplification can be performed.

The following is an example of the power amplifier invented by Ω. This will be explained in detail with reference to the following.

FIG. 1 is a circuit diagram showing the configuration of an embodiment (3) of a power amplifier according to the present invention. The emitter resistors 2a and 2b of these transistors la and lb are commonly connected to the output terminal 3,
A bias circuit (for example, a foot voltage circuit) 4 is inserted between the bases of these transistors la and Ib to flow an equal amount of bias current to these transistors 1a and 1b. This bias circuit 4 adjusts the bias current by 1% from a large value at which the transistors 1a and 1b are biased to class A (or super class) according to the output of a bias control circuit 10 (bias control means) to be described later.
Alternatively, these transistors la and lb are configured so that they can be switched from a small value of 2 to be biased to class B.

Next, the power supply 5a (voltage E,) and the power supply 6a connected in series are
(Voltage E2) is a power supply for supplying a positive power supply tolerance voltage of 1 B to the collector of the transistor 1a, and the power supply 5
The negative side terminal of a is grounded, and the connection point between the positive 11Ill terminal of the 'P48L source (4) 5a and the negative side terminal of the power supply 6a is connected to the transistor 1a through a diode 7a in the forward direction.
The positive terminal of t@l61L is connected to the collector of the transistor 1a via the switch circuit sat.

On the other hand, the power supply 5b (voltage E1) and the power supply 6b are connected in series.
('[pressure E2) is a power supply for supplying negative '#11 source voltage -B to the collector of the transistor 1b, the positive terminal of the power supply 5b is grounded, and the negative terminal of the power supply 5b and the power supply 6b The connection point with the positive side terminal of is connected to the collector of the transistor 1b through the diode 7b in the opposite direction, and
The negative terminal of transistor 1b is connected to the collector of transistor 1b via switch circuit 8b. The signal level detection circuit 9 detects the voltage e of the output signal obtained at the output terminal 3. When the absolute value of the voltage θ is less than a predetermined level set slightly smaller than the voltage θ. The detection signal is output within a predetermined period of time after the absolute value of the detection signal falls below the predetermined level.

The detection signal output from the signal level detection circuit 9 is sent to the bias control circuit 10 and the power supply voltage switching circuit 11 (Ilf
f, source pressure switching means). The bias control circuit 10 controls the bias circuit 4 by controlling the transistors la and lb when the detection signal is not supplied.
is biased to class A (or class AB), that is, the bias current is controlled to be 1 greater than the value, and when the detection signal is supplied, transistors la and lb are biased to class B. This is a circuit that controls the bias current so that the value becomes 2. Further, the power supply voltage switching circuit 11 opens both the switch circuits 8a and 8b if the detection signal is not supplied from the signal level detection circuit 9, and opens the switch circuits 8a and 8b if the detection signal is supplied between them. Both circuits are closed. Note that the terminal 12 is a ground terminal corresponding to the previous output terminal 3.

Next, to explain the operation of this power amplifier with the above configuration, time t1 at 2 in the time chart shown in FIG.
As before, the voltage e. When the absolute value of is below a predetermined level corresponding to the voltage range, that is, when a small signal is amplified, the signal level detection circuit 9 does not output a detection signal. Therefore this:l! Since the power supply blood pressure switching circuit 11 closes the switch circuits 8a and 8b, the voltages 1B and -B are 1 for the voltages +- and - of the power supplies 5a and 5b, respectively, and the diode 7a.

7b (see (a) in FIG. 2).

In this case, the bias control circuit 10 controls the bias circuit 4 so that the bias current becomes 1. In this manner, before time t1, transistors la and lb are biased to perform class A operation, and voltages 1K1 and -El are supplied as voltages 1B and -B. Next, at time t1, the voltage e. When the absolute value of exceeds the predetermined level, the signal level detection circuit 9 outputs a detection signal. Therefore in this case,
The power supply voltage switching circuit 11 closes the switch circuits 8a and 8gb, and as a result, the voltages +(E1+2) and (ml+"2) are supplied as the voltages 1B and -B. Note that at this time, the diodes 7&, 7b are in a reverse bias state.In addition, in this case, the bias control circuit 10
switches the bias current to 2 (more than 2 < more than 1). In this way, time 1. In this case, the biases of transistors la and lb are switched to perform B-line operation, and voltages 1B and -E are respectively increased. Next, at time t2, the voltage e. When the absolute value of the signal level detecting circuit 9 decreases below the predetermined level, the signal level detection circuit 9 stops outputting a detection signal at time t3 when a period T□ has elapsed from this time. Therefore in this case,
The switch circuits 8a and 8b transition from the closed state to the open state at time t3, and as a result, the voltages 10B and -B are decreased from 0 (Umako E2) and (E, 10E2) to +E1 and -Σ1, respectively. Ru. Also, at this time, the bias is increased from a value of 2 to a value of 1 for the current. In this way, at time t3, transistors la and lb are transferred from the class 3 bias state to the class A bias state, and 1B and -B are respectively decreased. Note that the period T1 is a voltage θ. This is provided to prevent the voltage from being increased or decreased more frequently than the bias current when the voltage is increased or decreased frequently. Thereafter, according to exactly the same operation, the voltage e is changed from the voltages 1B and -B and the bias current. It is increased or decreased according to the increase or decrease in the absolute value of.

In this way, according to this embodiment, if the signal level of the signal to be amplified is small, the power amplification stage is biased to class A and the power supply voltage is reduced, and if the signal level of the signal to be amplified is large, the power amplification stage is The power supply voltage can be increased while biasing the stage to class B. In addition, in the above embodiment, the timing at which the bias current is switched and the timing at which the voltages 10B and -B are switched are explained as being the same timing, but the timing at which the bias current is switched is the same as the timing at which the bias current is switched. The voltage is 10B in the current state.

-If the condition that B is always decreased is satisfied, then
It may be changed arbitrarily. For example, as shown in FIG.
may be shifted back by a period T2f from the timing at which is decreased. Furthermore, in the above embodiment, the bias current was explained as switching between transistors la and lb to perform class A operation or B line operation.
&, 1b can be switched to perform either Class AB or B-line operation, or Class A or Class AE operation, or can simply be switched without completely switching modes of operation. It may be increased or decreased.

Next, FIG. 3 is a circuit diagram showing a specific example of a power amplifier according to the present invention, and in this figure, parts corresponding to those in FIG. 1 are given the same reference numerals.

Therefore, the explanation will be omitted. In FIG. 3, the signal level detection circuit 9 detects the voltage θ of the output signal at the output terminal 3. , the same voltage θ. An absolute value circuit 13 converts the absolute value 1eo+ and outputs it, and compares the output 1eol of this absolute value circuit 13 with the reference voltage Vr, and if IQoI≧Vr, outputs a high level signal, and if l eel < v r A ratio s2 device 14 that outputs a ground level signal, resistors 16 to 18 connected in series between the output terminal of this comparator 14 and the base of a transistor 15), and a resistor 16.
A diode 19 connected in parallel with 17 and a resistor 16.
Capacitor 2 connected between the connection point of 17 and the ground point
0 and a PNP transistor 21 whose base is connected to the collector of the transistor 15.
o l (If Vr, the collector voltage of the transistor 21 becomes the ground level, 1θ. If 1≧Vr, the collector voltage of the transistor 21 becomes the high level, and l
θ. From the state of 1≧Vr to 1eol (transitioned to Vr-
When the time T1 determined by the resistance values of the resistors 16 to 18 and the capacitance of the capacitor 20 has elapsed, the transistor 21
The collector voltage of the circuit shifts from high level to ground level. The power supply voltage switching circuit 11 is an NPN driven by the collector current of the transistor 21.
) A transistor 22 and a PIP driven by the emitter current of this transistor 22) A run raster 23, etc., and if the collector voltage of the transistor 21 is at a high level, the PIP transistor 8 & (U) ↓・and NPN) transistor 8b is made conductive, and when the collector voltage of transistor 21 is at ground level, transistors 8a and 8b are made non-conductive. Thus, transistors ga and gb each correspond to the switch circuit 8IL18b shown in FIG. Bias control circuit 10
When a potential difference occurs between the positive terminal of the power supply 6a and the collector of the transistor 1a, that is, the transistor 8
A PNP transistor 24 is conductive when a is non-conductive, and becomes non-conductive when no potential difference occurs between the positive terminal of the power supply 6a and the collector of the transistor 1a, that is, when the transistor 8a is conductive; transistor 24
The NPN transistor 25 is driven by the collector voltage flow of the NPN transistor 25, which is conductive when the collector voltage of the transistor 25 is at a high level, and is non-conductive when the collector voltage of the transistor 25 is at the ground level. When the transistor 8IL becomes conductive, the transistor 26 becomes conductive, and when the transistor 8a becomes non-conductive, the transistor 26 becomes non-conductive (12). Bias circuit 4 is PN
P) Resistors 28 to 27 connected in series between the transistor 27 and the emitter and collector of the transistor 27
30, the emitter of the transistor 27 is connected to the output terminal of the constant current source 31, and is also connected to the base of the NPN transistor 321L that drives the transistor 1&, and the collector of the transistor 27 is connected to the output terminal of the constant current source 31. , an NPN transistor 33, and a resistor 34 in order to the negative terminal of a power source 6b, and also to the base of a PNP transistor 32b that drives the transistor 1b. In this bias circuit 4, when the transistor 26 becomes conductive, the collector-emitter voltage of the transistor 27 decreases, and the transistors la, lb
, while transistor 26
When the transistor 27 becomes non-conductive, the collector-emitter voltage of the transistor 27 increases, causing the bias current to increase.

(2) A terminal 35 connected to the base of the transistor 33 is an input terminal of this power amplifier.

(13) According to the specific circuit shown in FIG. 3, the same operation as the embodiment shown in FIG. 1 can be performed.

Next, FIG. 4 is a circuit diagram showing another specific example of the power amplifier according to the present invention. In this figure, the bias control circuit 10 has a voltage θ as shown in FIG. and voltage e such that when the absolute value of exceeds a predetermined level corresponding to voltage E1, the bias current becomes less than the value 2. If the absolute value of is below the predetermined level, the bias current is higher than the value
The bias circuit 4 is controlled so that xB>2). The power supply voltage control circuit 11 also includes a resistor 3 inserted between the positive terminal of t#6a and the base of the transistor 8a.
6 &, a Zener diode 37 & (Zener voltage Vz) inserted between the base and the output terminal 3.

Zener diode 37b (Zener voltage v”) inserted between the output terminal 3 and the base of the transistor 8b
, I"J base and the negative terminal of the power supply 6b, each having a resistor 36b inserted between the voltage e. and the negative terminal of the power supply 6b. When the Zener voltage Vz and the voltage e.
As shown in 0) in the figure, it is changed according to the voltages le and +Vzl.

However, the specific circuit shown in FIG. 4 can also provide the same effect as the embodiment shown in FIG.

In addition, in the examples and specific examples described above,
The voltages +E, -B and the bias current were mainly changed in steps, but these voltages +E, -
B and bias drawer: From the flow (a) and (b) in Figure 6
Each may be changed in an analog manner as shown in FIG.

As is clear from the above description, according to the power amplifier according to the present invention, bias control means and power supply voltage control means are respectively provided, and based on the signal to be amplified, when the signal level of the signal to be amplified is small, In this method, the bias amount of the power amplification stage is increased and the power supply voltage is decreased, and when the signal level is large, the bias amount is decreased and the power supply voltage is increased. In addition, large signals can be amplified with extremely high power efficiency, thereby achieving both a low distortion rate and a wide dynamic range.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing the configuration of an embodiment of the present invention, and FIG.
The figure is a time chart for explaining the operation of the same embodiment.
FIG. 3 is a circuit diagram showing one specific example of this invention, FIG. 4 is a circuit diagram showing another specific example of this invention, and FIG. 5 is a timetable for explaining the operation of the specific example shown in FIG. Chart, No. 6
The figure is a time chart showing another method of controlling bias current and power supply voltage in the present invention. la, lb...'Power amplification stage (transistor),
4...Bias circuit, 5"% 5 bs 6
a) 6 b...Power supply, 8a18b...
Switch circuit, 9...Signal level detection circuit, 10
...Bias control means (bar (16) bias control circuit), 11...Power supply voltage control means (
power supply voltage control circuit). Applicant: Nippon Musical Instruments Manufacturing Co., Ltd. (17) Figure 4 Figure 5

Claims (1)

[Claims] bias control means for increasing the bias amount of the power amplification stage based on the signal level of the signal to be amplified when the signal level is small and decreasing the bias amount when the signal level is large; Based on the above, the power supply voltage control means decreases the power supply voltage supplied to the power amplification stage when the signal level is small, and increases the power supply voltage when the signal level is large. A power amplifier with a characteristic of %.