JPS58114118A - Device controlling system - Google Patents

Abstract

PURPOSE:To reduce the number of steps to monitor a device efficiently, by providing a register, where different status data are set in accordance with processing conditions of the device, and a timer which monitors the time when a bit of this register has a prescribed polarity. CONSTITUTION:Status data stored in status registers REG of channels #0-#n are read through a bus (b) by a processing device MPU. Different processing states of each of channels #0-#n are indicated by respective bits constituting the register REG. The status signal read by the device MPU is set to a monitor register REG2, and respective bits of the register REG2 are monitored by timers T1-Ti. Polarities of the register REG2 are monitored by timers Tl-Ti to discriminate whether data indicates the ready state or not; and if the device is not ready, the device is restarted, and an overflow signal is set to an allocation register REG3 when a prescribed value is counted.

Description

[Detailed Description of the Invention] [Technical Field] The present invention monitors the processing status of a device, and when the device is in an empty state, a so-called ready state, a command is given to the device, and a bus connected to the device is This is related to device control methods for releasing occupancy.

<Prior art> In a line-connected system, a bus control device or MPU requests processing from a channel, monitors a busy signal or termination response generated from the channel, and at the end of processing, A device control method that requests the next process is known.

However, in such a method, the MPU reads the device status (hereinafter referred to as reading), determines whether the device is in an empty state, so-called ready state, and if it is not in the ready state, loops again and reads the device status. If the device fails, the MPU
′ program falls into an infinite loop.

To do this, generally, when a device is requested to perform a process, a specific timer is set, and in the routine that determines the status of the device, it is determined whether or not it has timed out, the device transitions to the ready state, and at 9 o'clock, the timer is set. A method of turning it off is adopted to prevent it from falling into an infinite loop.

Alternatively, prepare a software counter that counts the number of days that the status has been read, clear the counter when requesting processing, increment the status every time the status is incremented, and issue an error when the status exceeds a predetermined value. Technique 2-Processing techniques are also known.

However, the nine conventional methods described above have the disadvantage that they require a program to control a clock, timer, or counter, and require many steps in the program.

<Object of the present invention> An object of the present invention is to provide a device control method that can reduce the number of steps and efficiently monitor devices in order to eliminate the above-mentioned conventional drawbacks. To achieve this purpose, the present invention provides a hardware timer that automatically starts timer monitoring once the status data of the device is set. .

<Embodiment> FIG. 1 is a block diagram of an embodiment of the present invention, and FIG. 2 is an operation flowchart thereof.

In the figure, MPU is Tokoyoshiso&, b is bus, CH: #O~CH
#n is the channel, REGI is the status register, DE
C is a decoder, REG2 is a monitoring register + T1 to Ti are timers, ■ is an inverter, and REG3 is an interrupt register.

0 is an or gate.

The operation in FIG. 1 will be explained with reference to the second section.

The MPU reads the status stored in status register REG1 of channel CH#O via bus b. Status register REG1 indicates that each bit configuring register REGi is in a different processing state in channel CH$0. Correspondingly, it displays the status of all functional circuits of channel CH#0 (e.g. 0 and 1 (busy beep indicating that channel CH$O is executing processing), and generates a response to a request from the MPU. A response bit indicating whether or not there is a sense of security, or a bit indicating that transmission is in progress if channel CH$0 is connected to a line or the like.

The bit indicating that reception is in progress is set to each bit ff of register REG1.
) K is assigned and displayed.

The MPU reads the nine status data and sets it in the monitoring register REG2.

Timers T1 to Tn are provided corresponding to each bit of the monitoring register REG2, and the outputs of each bit of the registers RF and G2 are connected to each other. -1, start time monitoring. When the start terminal 3 is connected and the corresponding bit output is at %0, the data level of b, which is inverted by the inverter, is level %.
1'C) (It has a reset terminal P that is reset by serial number m.

Therefore, if the status data to be set in the register REGI is configured so that the bit of the channel CH$0 that is being processed is set to level 1, the status data set in the monitor register REGI will be set to level 1.
When the status data is set to 11, only the timer Tj corresponding to the timer Tj that is being processed operates, and the other timers are placed in the reset state 11.

After sectoring the status data into the monitoring register REG2, the MPU determines whether or not the status data indicates a ready state.
), return to the step of reading the device status again, and repeat in the same manner. When all processing is completed in 0 channel CM well 0 and the state is ready, that is, a state in which processing can be accepted, that processing is completed. The data of the bit corresponding to level XX1# is set to level %Ol.

As described above, 1'1llPU operates according to the routine shown in FIG. 2, and the relevant bit becomes level %Ol, which indicates a good state and is matted in the monitoring register REG2. As a result, the timer Tj, which monitors the processing status at the level %IN, is automatically reset and ends the timer monitoring. Meanwhile, the timer reaches a predetermined value, for example, the overall performance of the device. At the start of fy, when a predetermined value set by the MPU is counted via a path not shown,
7p-, and the signal is set in interrupt register REG3. Each bit output of the allocation register REG3 is supplied to the SOMI'MPU via an OR gate O as an allocation signal.

The fiMPU uses a known interrupt processing method to
The register REG3 is read, the cause of the interrupt is analyzed, and in the case of this embodiment, error handling is performed.

In the above embodiment, only the channel CH$O was described as one of the devices, but the same applies to other channels or devices as long as the MPU requests processing.

Furthermore, although the MPU has been described as requesting one process to a channel, it may also request other processes while one process is being executed.

In this case, two timers will be operated.In addition, it was explained that the predetermined value of one timer is set when the operation of the entire device starts, but at any given time, one timer is set at that time. Nine predetermined values may be set corresponding to the processing.

As a result, the timer itself can be provided with versatility, and it is possible to achieve the effect of not increasing the size of the device.

<Effects> As explained above, according to the present invention, timer monitoring is performed in one step by simply writing to the monitoring register, so the program of the processing device does not need to be particularly aware of the timer. Only the step that determines whether processing is complete is required. In other words, the processing effect can be improved.

[Brief explanation of drawings]

1 and 2 are a block diagram and a flowchart of an embodiment of the present invention. In the figures, MPU is a processing unit, CH#O to CB are channels, REG-IU status register, and REG2 is a monitor 4; 1) Registers, T1' to πi are timers, REG3 is an interrupt register, and 0 is an open ψ゛ gate.

Claims (1)

[Claims] A device control method that includes a processing device and a device that performs processing in conjunction with the processing device, monitors the processing status of the device, and requests processing when the device is in an idle state. A register in which different status data is set depending on the situation, and a timer connected to the output of each bit position of the register to monitor the time when the corresponding bit of the register reaches a predetermined polarity Kl are provided, and the device processing corresponding to the status data,
Device control method 0 characterized by starting and monitoring a mosquito timer