JPS58111529U - automatic frequency control circuit - Google Patents

automatic frequency control circuit

Info

Publication number
JPS58111529U
JPS58111529U JP754282U JP754282U JPS58111529U JP S58111529 U JPS58111529 U JP S58111529U JP 754282 U JP754282 U JP 754282U JP 754282 U JP754282 U JP 754282U JP S58111529 U JPS58111529 U JP S58111529U
Authority
JP
Japan
Prior art keywords
aft
voltage
circuit
automatic frequency
frequency control
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP754282U
Other languages
Japanese (ja)
Inventor
神津 光宏
Original Assignee
株式会社東芝
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 株式会社東芝 filed Critical 株式会社東芝
Priority to JP754282U priority Critical patent/JPS58111529U/en
Publication of JPS58111529U publication Critical patent/JPS58111529U/en
Pending legal-status Critical Current

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  • Television Receiver Circuits (AREA)
  • Channel Selection Circuits, Automatic Tuning Circuits (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図は従来のチューナ回路、映像中間興竺回路、自動
周波数制御(以下AFT)回路のブロック図、第2図は
チューナ回路内のAFT回路に印加されるAFT制御電
圧特性(8字特性)を示す特硅図、第3図はAFT制御
電圧発生回路の構成を示す回路図、第4図は電源電圧の
変動に対するAFT特性の変化を示す特性図、第5図は
同調調整時の電源電圧変動に対するAFT引込範囲の変
化を示す特性図、第6図は本考案の実施例に係るAFT
制御回路を示す回路図、第7図は第6図の回路において
可変抵抗を変化させバ場合の8字特性の変化を示す特性
図、第8図は同特性のAFT引込範囲を示す特性図、第
9図番j本考案の他の実゛施例に係るAFT制御電圧処
理回路を示す回路図である。 ”− ,1・・・・・・アンテナ端子、2・・・・・・チュー
ナ回路、31・・・・・・PIF/AFT回路、4・・
・・・・AFT制御電圧処理回路、5・・・・・・AF
T動作動作子・・・・・・AFTディフィートスイッチ
、8・・・・・・定電圧電源回路、9・・・・・・電圧
安定化回路。
Figure 1 is a block diagram of a conventional tuner circuit, video intermediate circuit, and automatic frequency control (AFT) circuit, and Figure 2 is the AFT control voltage characteristic (character 8 characteristic) applied to the AFT circuit in the tuner circuit. Figure 3 is a circuit diagram showing the configuration of the AFT control voltage generation circuit, Figure 4 is a characteristic diagram showing changes in AFT characteristics due to fluctuations in power supply voltage, and Figure 5 is power supply voltage during tuning adjustment. A characteristic diagram showing changes in AFT pull-in range with respect to fluctuations, FIG. 6 is an AFT according to an embodiment of the present invention.
A circuit diagram showing the control circuit, FIG. 7 is a characteristic diagram showing the change in the figure 8 characteristic when changing the variable resistance in the circuit of FIG. 6, and FIG. 8 is a characteristic diagram showing the AFT pull-in range of the same characteristic. FIG. 9 is a circuit diagram showing an AFT control voltage processing circuit according to another embodiment of the present invention. "-, 1... Antenna terminal, 2... Tuner circuit, 31... PIF/AFT circuit, 4...
...AFT control voltage processing circuit, 5...AF
T operation element: AFT defeat switch, 8: Constant voltage power supply circuit, 9: Voltage stabilization circuit.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] チューナ回路の同調ずれを検出した電圧を差動アンプに
て増幅して取り出し、各差動出力を合成してAFT制御
電圧を形晟し、千れを局部浄振回路に印加して前記同調
ずれを補正すると共に、選局中にAFT動作を一時的に
解険するためにAFTディフィートスイッチで前記各作
動出力を短絡してAFT基準電圧を得、この電圧、に基
づいて同調ポイントより上側及び下側の引き込み範囲が
決定される自動周波数制御回路において、前記AFTデ
ィフィートス゛イツチの一端に供給する固定電圧回路を
設け、から、前9AFTデイフイ゛−゛トスイツチの他
端に可変できる合成比でAFT制御電圧・を印加できる
ように構成し、前記選局中のAFT解除時には前記局部
発振回路に前記固定電圧回路の電圧が供給されるように
したことを特徴とする自動周波数制御回路。
The voltage that detects the out-of-tuning of the tuner circuit is amplified and taken out by a differential amplifier, the respective differential outputs are combined to form an AFT control voltage, and the voltage is applied to a local vibration circuit to detect the out-of-tuning. In order to correct the AFT operation and temporarily release the AFT operation during channel selection, the AFT defeat switch short-circuits each operation output to obtain the AFT reference voltage, and based on this voltage, the voltage above the tuning point and In the automatic frequency control circuit in which the lower pull-in range is determined, a fixed voltage circuit is provided to supply one end of the AFT defeat switch, and a variable synthesis ratio is provided to the other end of the front nine AFT differential switches. An automatic frequency control circuit characterized in that the automatic frequency control circuit is configured to be able to apply an AFT control voltage, and when the AFT is canceled during the channel selection, the voltage of the fixed voltage circuit is supplied to the local oscillation circuit.
JP754282U 1982-01-25 1982-01-25 automatic frequency control circuit Pending JPS58111529U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP754282U JPS58111529U (en) 1982-01-25 1982-01-25 automatic frequency control circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP754282U JPS58111529U (en) 1982-01-25 1982-01-25 automatic frequency control circuit

Publications (1)

Publication Number Publication Date
JPS58111529U true JPS58111529U (en) 1983-07-29

Family

ID=30020287

Family Applications (1)

Application Number Title Priority Date Filing Date
JP754282U Pending JPS58111529U (en) 1982-01-25 1982-01-25 automatic frequency control circuit

Country Status (1)

Country Link
JP (1) JPS58111529U (en)

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