JPS58111291A - Induction heating cooking device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field of the Invention The present invention is directed to, for example, cooking food in a cooking pot by heating the cooking @ which would otherwise be done under load using an fj 6-circle temporary surrounding magnetic field by heating it exclusively at vj. Regarding vj4 heat cooking benefit.

Technical Background of the Invention Conventionally, in this woodcutter's induction heating cooker, the heating output was established by controlling the deity of the input power, and for this reason, the input X current and the reference value at one point were A no-load calculation was possible by comparing the results.

Problems with the Background Art However, recently, induction heating cookers with continuously variable heating output have been developed and are being put into practical use. In this case, there is a problem in that setting a reference standard for comparing the human power current when detecting a change in the heating output is extremely complicated, and reliable no-load detection becomes a problem.

Purpose of the invention This invention was made in view of the above circumstances.
The purpose is to provide a rice husk induction heating cooker with excellent reliability that enables reliable load state detection without being affected by changes in human power current.

SUMMARY OF THE INVENTION The present invention detects the ratio of the input current to a reference value obtained from the output of an inverter circuit.

Embodiment of the Invention Hereinafter, an embodiment of the present invention will be described with reference to the drawings. In the WJ1 diagram, 1 is a bladder connected to an AC power source, and this glove 1 is connected to a fan motor 4 for cooling the transistor via a current fuse 2 and a power switch 3.
and transformer 5 are connected. Furthermore, the above-mentioned current is connected to the heating coil 9 and the inverter via a DC power supply circuit 15 consisting of a rectifier circuit 6 of a diode prep, a check coil 1, and a smoothing capacitor 8 via a &-Z 2 and a power switch Jl. A series circuit with circuit 10 is connected. This inverter circuit 10 has a single-ended tie fO configuration mainly consisting of NPN transistors 10* and 10b. A capacitor 11 and a diode 12 are connected in parallel to the inverter circuit 10, and the capacitor 11 and the heating coil 9 form a series resonant circuit.

On the other hand, 20 is a drive circuit, and this drive circuit 20 turns on and off the transistors of the inverter circuit 10 by the output of the oscillation circuit GO supplied through the output setting circuit 40t. The output voltage of the DC power supply circuit 15 and the collector voltage of the transistor in the inverter circuit 10 are each supplied to a feedback circuit wr80, and the oscillation circuit 60 is activated by this feedback circuit 1f)K. Tsu°shikai heating coil 9 and con 7"7"jl
Together with I - It is the same time as the J14J Jokei and the 60th year of the company's 60th year. 40 is divided into 100 outputs and the set output is set by the output setting circuit 120.

Further, 140 is a human-powered -ηC power supply circuit, which is provided in the connection line between the electric power switch 3 and the ML power supply circuit 15. The human power current is detected by the 41u' lance 141,
This is the voltage 1F that corresponds to this human power current. In this input current detection circuit, the output of &140 is sent to the small article load detection circuit w&160 and the A constant #@, ω1 detection circuit 180. Small shell what Shinji times kj160 is in-9-
The output voltage of the transistor collector 10 connected to the voltage circuit 10 is set to be W for generating a high voltage inside the pressure regulator, and the output voltage of the detection circuit 140 is compared with that pressure. Depending on the stiffness ratio and softness, you will know whether the load of the cooking net is less than a foot. The abnormal current detection circuit 180 detects whether or not the load current is abnormal based on the output of the human power redundancy detection circuit 140. Therefore, when the small object load detection circuit 160 detects a shellfish with a size smaller than a pair of shoes, and when the abnormality flow detection path 180 detects an abnormality in the load current, the start/stop circuit 200 detects an abnormality in the load current.
A start/stop command is supplied from the start/stop circuit 200 to the output setting circuit 40. Further, the start/stop circuit 200 also responds to the detection output of the overheat detector 220. This overheat detection circuit 220 instructs the start/stop circuit wI200 to that effect when the temperature of the load exceeds a certain level. From this power supply circuit 240 to the upper drive circuit 20, the output setting circuit 4o, the generator circuit 60, the feedback circuit 80, the small load detection circuit 160 and the abnormal current detection circuit 180, respectively. Voltage is now available.

FIG. 2 specifically shows FIG. 1. In FIG. 2, a wcm circuit 240 rectifies the secondary output of the transformer 5 by %241. ! 42, smoothed by smoothing capacitors 243 and 244, and the DC voltage is transferred to the bus A,
0 and between busbars B and C, respectively.
The DC voltage obtained between the bus @A and 0 is converted into a constant voltage by an NPN transistor 245, a resistor 246, and a constant voltage diode 247, and the voltage is supplied between the bus and 0. Thus, the bus lines A and C are connected to the drive circuit 20, the output setting circuit 40, the oscillation circuit 60, and the output display circuit 120. Further, bus line B is connected to inverter circuit 10 . Furthermore, mother Ii1! D is a drive circuit 20, an output setting circuit 40, an oscillation circuit 60, and a feedback circuit S
O, connected to the output display circuit 120, the load current detection circuit 140, the small object load detection circuit 160, the abnormal current detection circuit 180, and the start/stop circuit 200.

The oscillation circuit 60 is a so-called unstable multi-giver, and includes resistors 61, 62 and (J:ry f resistor 6).
Connect the series circuit of S to bus A, Cf15, and resistor 6
The voltage obtained at the interconnection point of 2 and capacitor 6J is applied to the inverting input (-) of comparator 640. Also, resistance 6
A series circuit of 65 and 66 is connected between the bus line and 0, and the interconnection point of the resistors 65 and 66 is connected to the output terminal of the comparator 64 via a resistor 67. Furthermore, the interconnection point of the resistors 65 and 66 is connected to the non-inverting input terminal (+) of the comparator 64. The output terminal of the comparator 64 and the resistors 61 and 62
A diode 68f of the illustrated polarity is connected between the interconnection point of .

The output setting circuit 40 includes a semi-fixed resistor 41, a variable resistor 100 which is the output setting operation section, and a resistor 42 to form a series circuit.
IIk continued. Furthermore, a series circuit of resistor 1 (4J) and capacitor 44 is connected to mother@D.

0, and the interconnection point between the resistor 43 and the capacitor 44 is connected to the interconnection point between the variable resistor 100 and the resistor 42 via a diode 45 of the illustrated polarity. Then, the voltage obtained at the interconnection point between the resistor 43 and the capacitor 44 is supplied to the non-inverting input terminal (+) of the comparator 46 . The oscillation circuit 60 is connected to the inverting input terminal (-) of the comparator 46.
The resulting voltage is supplied to the interconnection point between the output cap resistor 62 and the capacitor 63. In addition, a series circuit of resistors 47, 411 and a diode 49 is connected between the bus line 0 and the interconnection point between the resistor 48 and the constant voltage diode 49 is connected to the output terminal of the comparator 46. The voltage obtained at the interconnection point between the resistor 48 and the diode 49 is supplied to the drive circuit 20 via the resistor 50.

The drive circuit 20 connects the resistors 21 and 22, the collector and the output of the NPN transistor 23, and the series circuit of the resistor 24, and supplies the output of the output setting circuit 40 to the base of the transistor 230. do. Furthermore, a series circuit between the 1 resistor 25 and the collector-emitter of the NPN transistor 26 is connected to the mother @A, Cl%1ll.
Connect K. Then, the emitter of the transistor 23 is connected to the base of the transistor 2# through the resistor 21, and the transistor 260 is connected to the bus line C through the resistor 28.
K11 continues. Further, the series circuit between the transistor vine and the collector of the PNPN upper type transistor 29, the resistor 30, the diode JJ, and the NPN type transistor sjo prector and emitter are connected to the motherboard -A and Cf1aK. The transistor 290 is then connected to the resistor 21.210 interconnection point. NP at the collector of transistor S2
The collector of N-type transistor 33 is connected and the emitter of this transistor JJ is connected to transistor 120 pace. Furthermore, a parallel circuit of a resistor 34 and a capacitor S5 is connected between the pace of the transistor SJ and the collector of the transistor 21.

The inverter circuit 10 is an NPN transistor 10**
10b, 10tt, 10a and diode-F10@, J
Configure a single-ended ino circuit, and drive each transistor with an output of 20 times and a casing resistor of 30
The switching operation is performed by the voltage obtained at the interconnection point between the diode S1 and the diode S1.

The return line 80 connects a diode 81 and a resistor #20 to the bus line and 0, and connects the collector voltage of the transistor in the inverter circuit 10 to the interconnection point between the diode 11 and the resistor 82. 83. Then, the voltage obtained at the interconnection point is supplied to the non-inverting input terminal (+) of the comparator a4. The inverting input terminal (-) of this comparator 14 is connected to the motherboard -CK through a resistor 85.
The output voltage of the DC current Il @ path 15 is connected to the interconnection point between the inverting input terminal (-) and the resistor 1j through the resistor 86.
I will try my best to supply it. Furthermore, the output end of comparison fi1a4 is
The mother rock DK is connected through the resistor 81, and the resistor 88
, the mother WM via the capacitor l# and the resistor #0 in series.
Connect to D. At the interconnection point between the capacitor 8# and the resistor 90, a PNP type F transistor 91 is connected.
! Next, a series circuit of resistors 91 and 91 is connected to the bus line through the construction and collector of this transistor 91, and Cl51
Connect to 1. Then, the voltage obtained at the interconnection point of the resistors ox and sx is supplied to the inverting input terminal (-) of the comparator 940. The non-inverting input terminal (+) K of this comparator 94 is supplied with the voltage obtained at the interconnection point of the resistors 47/411 in the output setting circuit 40. Thus, the output terminal of comparator 94 is connected to the output terminal of comparator 64 in oscillation circuit 60.

The input current detection circuit 140 includes a resistor 141°141.14
1 series circuit is connected to the mother@D, C gate, and its resistance 1
Capacitors 144 and 141 are connected in parallel to 42 and 143, respectively. Then, the resistor 142 and the capacitor 14
4 and the current transformer 14 through the conductor t141r, resistor 146 and diode 141t in the O parallel circuit.
Connect the output end of 1.

Abnormal current detection circuit # & J 410 has a resistance of 181° and 182°.
, Ill are connected between the motherboards D and C, and the voltage applied to the interconnection point of the resistors 1111 and 182 is supplied to the non-inverting input terminal (+) of the comparator 184.
The input current detection circuit 14 is connected to the inverting input 4 (-) of 84.
The voltage obtained at the mutual 1iIIkWc point of the diode 148 and the capacitor 144 at 0 is supplied.

The small load detection circuit 160 includes a capacitor 161 and a resistor 1.
One end of the parallel circuit with i2 is connected to the bus C, and the collector voltage of each transistor in the inverter circuit 10 is supplied to the other end of the parallel circuit through a diode 163 and a resistor 1fr4 in series. Therefore, a resistor of 1 ml is connected between the upper parallel circuit and the resistor 164 at the interconnection point number @C.
1i6 and a semi-fixed resistor 161 in series 1gl path ti1. A capacitor 1-8 is connected in parallel to the semi-fixed resistor 161. Then, a series circuit of a resistor 161 and a capacitor 110 is connected between the movable layer of the semi-fixed resistor WLIgF and the mother 4 IC, and a diode 17/I is connected to the resistor J##.
Connect to T-Niyu-Chang. Resistor 1-# and capacitor ivy
The voltage obtained at the interconnection point with 112 is applied to the inverting input (-) of the ratio Ill plow 172, and the non-inverting input (+) of this comparator 112 is connected to the input voltage lit@Dice N- in the knowledge circuit 140. The resulting voltage is provided at the interconnection point between the node 148 and the capacitor 144. Further, the voltage obtained at the output terminal of the comparator 4GO in the output setting circuit 40 is supplied to the non-inverting input terminal (+) of the comparator 113, and this comparison a xrsO inverting input terminal <-)? C supplies the voltage obtained at the interconnection point of the resistors 18; t, 183 in the abnormal current tIL familiarization circuit 780.

The start/stop circuit 200 includes a predistribution overheat detection device that responds to the temperature of the load (for example, a thermostat) 110, and a resistor of 20 J.
1 and capacitor ZOX's direct review wre mother i1D,
Between 0 and 0. Resistor 1 for con f 7 f 101
Connect 04 in parallel. Then, the voltage obtained at the interconnection point between the resistor 202, the capacitor f101, and the parallel circuit of the resistor 204 is supplied to the non-inverting input terminal (+) of the comparator 204.

Kono ratio @ @ z o 4 (D inversion input 111 (-) K C abnormal current detection (B) resistance 181, 1 in path 1110
The resulting voltage is supplied to 82 mutually enriched points. Therefore, the output nA of the comparator 204 is transferred between the resistor 4J and the capacitor 44 in the output display circuit 40! Connect to Ik wire point.

The output display circuit 120 includes a light emitting diode 121 connected to a resistor 12 for displaying whether the heating coil 9 is in operation or not.
2 and the collector of the NPN type transistor fill are connected between the bus bar M and C through the connector in series. Then, the conductor of transistor IJJ is connected via resistor 124 to a point of intersection between resistor 43 and capacitor 44 in output path 40. In addition, a light emitting diode 125
, 125. ...125 each resistance 111.126
．． ...Level meter JxrK*lIl via 126
And these 1gIwI'fr mothers.

*fi between C. The level meter 121 receives as input the voltage obtained at the mutual connection point of the variable resistor 100 and the resistor 41 in the construction circuit 40, and depending on the level of the input voltage, each of the light emitting diodes 125, 115, .・
.125 is operated selectively, and uses, for example, a Toshiba level meter IC called TM7655P.

Next, the operation in the above configuration will be explained.

First, load knob l111II for heating coil 9!
Set the pot (not shown) and set the variable resistor 10.
0 to set the output tube and turn on the power switch 1.

Then, in the departure corral 60, as shown in FIG.
When the photovoltaic voltage V@ is compared to the voltage Vr·f obtained at the interconnection point of resistors 65 and 66 when the photovoltaic sensor 6J is photovolted through resistors 61 and 62, the output of comparison -64 becomes a low voltage. , 11 resistors gg and gy are connected in parallel via the power line (not shown) of the ratio e converter 64. In other words, the voltage input to the non-inverting input terminal (+) of the p1 ratio IIR device 64 becomes Vr@fl, which is lower than Vr@fl. Then, the photoelectric voltage V@ of the capacitor 630 is discharged through the resistor 62, the diode 68, and the power supply line of the ratio IIR device 64. In this way, when the photoelectric voltage ve of the capacitor 63 becomes one less than the voltage Vr@fz, the photovoltage of the capacitor 630 is started, and thereafter the capacitor teraO light and discharge are repeated. At t9, the photoelectric voltage we of the capacitor 63 becomes the oscillation output.

On the other hand, in the output display circuit 40, FIG.
As shown, in response to the operation of the variable resistor 100, the voltage from the upper limit 1 to the lower limit e is applied to the non-inverting input terminal (+
). and the ratio IRWid10 inverting input 3
1111(-) is supplied with the oscillation output of the oscillation circuit @ie, that is, the charging voltage V· of the capacitor 630. As shown in Figure #g4, the output of the comparator 46 has a period T.
The on/off duty is determined based on the operation of the variable resistor 100 (depending on the output setting value). In this case, the period T is designed to be, for example, 50 μs.

Therefore, the drive circuit 20 operates the inverter tg11 &
IO transistor turns on and off, heating coil 9
fart? I6j! l1rI! The L current is supplied and the damping magnetic field emitted from the heating coil 9 is applied to the I4 block steel, and the JIIIfi/4 generates eddy current loss and self-heats, heating the food.

At this time, the collector voltage VX of the transistor in the inverter circuit 10 and the output voltage vy of the DC power supply circuit IIi as shown in FIG. 5(a)K are respectively supplied to the feedback circuit @go. Therefore, the result (b) approximately 80 performs the following operation, that is, as shown in j15wJ(b), the collector voltage V voltage g1
Further, il[tIL output voltage Vyt is converted into voltage 3 by resistance zs and aiyc. Then, by comparing the voltage gtygst- in the comparator 84, a signal t- shown in FIG. This signal is differentiated by a differentiating circuit composed of resistors aa and eo, a capacitor 89, a transistor 91, etc., and becomes a signal having a time width t1 as shown in FIG. 5(d). This differential signal is voltage-divided by resistors 92 and 93 to become a signal at the level shown in FIG. The non-inverting input terminal (+) of this comparator 94 is supplied with the output signal of the output t & foot rotation wI 40 (shown by broken - in FIG. 5()). In this way, as shown in FIG. 5(f)K, a signal that becomes low level for a time '1 Mts (twits) is output from the comparator 94, and is supplied to the firing circuit 60 as a signal. Therefore, the ratio V
When the output of the comparator 64 becomes low level, the resistor 66°61 in the Q circuit 60 is connected to the cap line KIIIkvc through the power supply line of the comparator 94, and the non-inverting input 4 (+
) is forcibly reduced to Vrst@. Taking this as a trigger, the output of the ratio I2 device 64 becomes logic @0.
9, the photoelectric voltage V of the capacitor 6S is discharged through the power supply line of the comparator 64. Then, when the photoelectric voltage ve becomes less than the voltage Vr@, the photoelectric voltage of the capacitor 63 starts again. That is, the oscillation circuit 60
The generated output is the signal 9 shown in Figure 5-), whose frequency is synchronized with the actual loss frequency due to the power I heating coil 9, capacitors 11 and K, and the loss in the inverter circuit 10 is small. Switching [Can be done.

here,#! Figure 6 (,) shows the change in the collector voltage Vx of the transistor in the inverter circuit @10. That is, at the maximum set output, the change is as shown by the dashed line in the figure, and at the minimum set output, the change is as shown by the solid line in the figure. By the way, the collector voltage VX (MAN
) and the output voltage V7 of the DC power supply circuit MJJ is β.
At p1, as described above, at the intersection point β, a z4 pulse with a time width t1 as shown in FIG. Also, what is the intersection between the collector voltage VX (Mlll) at the minimum set output and the output voltage vy of the DC power supply 1@Ill? So, the intersection point/1 is time + 1i! A pulse of i t 1 is generated, and in synchronization with it, the generator circuit 60 is activated. As is clear from FIG. 6(a), at this minimum set output, the intersection! has a time difference of α with respect to the zero potential point of the collector voltage VX. Therefore, the r point 't
-4, the transistor 10a turns on and turns off in a short time (because the set output is at the minimum, the transistor 10a
the on-time of a is short), and if its off-point exists within the α time, the capacitor 1 forming a resonant circuit
1 to each transistor of the inverter circuit 10, causing problems such as interfering with the valley transistors, increasing power loss, and increasing noise during switching. Therefore, in the present invention, such ffL value is made to depend on the discharging time constant of the capacitor 6J in the oscillation circuit 60 and the change in the voltages e1 to e08 in the output setting circuit 40.

That is, I@6 (b) shows the change in the photoelectric voltage V@ of the capacitor 63 when the set output is maximum and when the set output is minimum. As is clear from this, the photoelectric voltage We (Mill) at the minimum set output is at the intersection! It intersects with the enemy set voltage es with a delay of r time from , and the point of intersection approximately coincides with the intersection of the photoelectric voltage VC (M) at the maximum set output and the set voltage e1 at the maximum. If it is the intersection of the photoelectric voltage V@(MAN) and the maximum setting voltage e1, the fall of the output voltage of the output setting circuit 400 will be repeated, that is, the off point of the transistor 10a will be at the maximum setting output of -1, as well as at the maximum setting output. Even at a small time, the zero potential point of the collector voltage VX is sufficiently exceeded], and an abnormally large electric current t is applied from the capacitor 11 to each transistor of the inverter circuit 10.
LL never flows.

Next, 1. No-load detection will be described. current transformer 14
1 outputs a voltage t- corresponding to the power supply current, and this output voltage is rectified by the load current detection igJ circuit 140. By the way, the input voltage R detection circuit 140 includes resistors J4J, J4J,
Since a small odd bias voltage is applied by J4J, the output of the comparator 112 in the small load detection circuit 160 is always logic when the power is turned on (when the inverter circuit 10 is not operating). It is constructed to maintain a distance of 11m. The small item negative # detection circuit 160 first connects the diode 1
63, resistors 164, 162, and capacitor 161 to step down and smooth the collector voltage of the transistor in the inverter circuit 10, thereby obtaining a voltage that is not affected by the set output but is proportional to the power supply voltage.

This voltage is compared to J 7 jK, output setting time w1
Changes in synchronization with the output of 4#. This voltage is then smoothed by a capacitor 16g. In a fist, voltage Vk of capacitor 9168 and load current detection 1gl
The relationship with approximately 1400 output voltage v1 is shown in FIG. Thus, voltage Vk is articulated by semi-fixed resistor 161 to a potential lower than voltage Vl, and is supplied to comparator 172 as a reference voltage. In this way, the output voltage v1 of the input mfL detection circuit 140 and the reference voltage Vk are compared in the comparator 172. When the load size is below a certain level, one voltage Vl becomes the reference voltage V
k or less, and the output of the ratio @91711 becomes logic ``01''.Then, the charging voltage of the capacitor 20S in the start/stop (b) path 200 is discharged, and the output of the comparator gos becomes logic ``0''. .The output of the comparator 205 is logic 1.
01, the capacitor 4 in the output setting circuit 40
A discharge path for 4 is formed, and the 1st cycle "θ'" is generated without being affected by the output of the gravity setting circuit aoFi oscillation circuit 60.
Maintain output. Therefore, the inverter circuit w110 does not operate, and the heating operation is prohibited. In the case of jin, the reference voltage Vk
In order to enable sufficient discharge of the capacitor 201 without being affected by changes in
Ivc is configured. Note that when the power is turned on, the start/stop circuit 200 starts charging the capacitor gos, and when the photoelectric voltage is sufficiently high, the output of the comparator 205 becomes
"1", the output voltage Vr in the non-inverting input terminal voltage tube failure circuit 60 of the comparator 46 in the output & constant circuit 40
@f1 or more, thereby enabling the operation of the inverter circuit 10. Then, when the load is abnormal as mentioned above,
Alternatively, when the load temperature rises abnormally, the photoelectric voltage discharge of the capacitor 203 is compared and the output of the capacitor 205 is set to logic ""01.
This prohibits the heating operation (K).

Furthermore, when the detected load current becomes abnormally large, the output of the comparator 184 in the normal current flL detection circuit 180 becomes logic ``O#'', and the heating operation is prohibited by the start/stop circuit 200.

On the other hand, in the output display circuit JJO, when the output coil 9 is conductive, the photoelectric voltage of the capacitor 44 in the output setting circuit 40 turns on the transistor JJJ and operates the light emitting diode P121. In addition, the level meter 1 is adjusted according to the set voltage based on the operation of the variable resistor 100.
21 is activated, and an arbitrary light emitting diode 125 is activated according to the set output. .

Next, the operation with respect to fluctuations in the AC fLIlE source voltage will be described.The charging voltage V of the capacitor 63 in the 0 failure circuit 60 is expressed by the Hiroshita equation.

V*mjC(1-#”) Here, E is the applied voltage, C is the capacitance of the capacitor 63, and R
It is a combined resistance of h resistance 61.62.

That is, the charging voltage V@ of the capacitor 63 is the applied voltage I
This is done with a time constant of 01 for . In this case, the applied voltage E is the bus bar.

Since it is obtained between 0 and 0, it corresponds to the AC power source voltage, and thus the charging voltage of the capacitor 63 Ft-V@% corresponds to the AC source voltage. Figure 8-) shows the change in the photoelectric voltage V@, and as the AC power supply voltage increases, the time to reach Vr@fs from vr@fm becomes shorter as shown in the figure, and the AC power supply voltage As the value becomes lower, the time taken to reach Vr@fl from Vrvfl becomes longer, as shown by the solid line shown or the two-point @ line shown in the drawing. At this time, if the charging voltage of the capacitor 44 of the output setting circuit 40 based on the operation of the variable resistance 200 is (b) , (
@) , (d). However, the drive pulse width f of the inverter circuit 10 can be maintained substantially regardless of fluctuations in the AC power supply voltage, and therefore fluctuations in output can be suppressed. Here, the table below can be obtained by experimenting with changes in the force state due to fluctuations in AC power supply voltage, and it can be seen that the inventive circuit has less output change than the conventional circuit. .

In this way, the reference m is obtained from the collector voltage of the transistor in the inverter circuit 1o, and the load condition is detected by comparing the reference value, which changes in a circular pattern, with the input current. Highly reliable load state detection can be performed.

It should be noted that the present invention is not limited to the above-mentioned embodiments, and it goes without saying that various modifications can be made without changing the spirit of the invention.

Effects of the Invention As described above, according to the present invention, it is possible to provide a highly reliable fermentation heating cooker that can reliably detect the load state 114 without being affected by changes in input current.

[Brief explanation of the drawing]

The drawings show an embodiment of the present invention (FIG. 1 is a block diagram schematically showing the overall configuration of the control circuit, FIG. 2 is a block diagram specifically showing the #1!1 diagram, #I3 is a signal waveform diagram to clarify the operation of the oscillation circuit, and Figure 4 (
a), 佽) are signal waveform diagrams to explain the operation of the output setting circuit, and circuit diagrams 5(a), 伽), (a),
(d), (・), (f), and (g) are signal waveform diagrams for explaining the operation of the feedback circuit, respectively. Figure 6 (a), (b), and (@) are respectively at the time of output change. Maintenance for the inverter circuit! Fig. 7 is a signal waveform diagram to explain the function, and Fig. 7 is a characteristic diagram to explain the operation of the input 1iLfi detection circuit and the small tube load detection circuit.
FIGS. 8(a) and 8(a) are signal waveform diagrams for explaining the operation of the development circuit with respect to power supply voltage fluctuations, respectively. 9... Heating coil, 10... Inverter circuit, 10
* p J Ob , 10 e , 10 d ・”
NPN transistor, 11... capacitor, 15.
... DC power supply circuit, 20 ... Drive circuit, 40 ... Output setting circuit, 60 ... Unstable multivibrator (spring circuit), 80 ... Feedback circuit, 140 ... Input current detection circuit, 160... Load detection circuit (small object load detection circuit), iao... Abnormal current detection circuit, 20o... Start/stop circuit. Patent attorney Suzue Takehiko 3rd @ Figure 4 Figure 5 6ml Figure 7

Claims (1)

[Scope of claims] It is equipped with an inverter circuit and a capacitor that is connected in parallel to the inverter (b) path and forms a thread layer circuit together with the heating coil, and the heating output is continuously varied by driving and controlling the inverter circuit. In the induction heating cooker that can be used, an input current detection circuit is provided to detect the AC input current to the DC'Kamehan circuit, the output of this input current detection circuit is compared with a reference value, and this ratio IIRM result is calculated as the load condition. The invention is characterized in that a load detection circuit for each detection is provided, and a reference value of the load detection circuit is obtained from the output of the inverter circuit. Induction heating cooking described in Section 1 of Section & 5.