JPS58108928A - Power distributing device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a power distribution device, particularly a power distribution device having a power supply output for a long-time continuous load and a short-time load, and which functions as a long-time continuous load while the short-time load is being used. The present invention relates to a power distribution device that can use both loads at the same time without completely stopping the load and without causing the total power of both loads to exceed a predetermined value by using the load for a short time.

Traditionally, if one load tries to temporarily use the other load while the other load is in use, one load is completely disabled during the temporary use of the other load, and the power supply is automatically temporarily used. There is a power supply switching device that allows two large-capacity loads to be used at the same time without exceeding the contracted power agreed between electric power companies by setting the load to only one load.

However, if one of the loads is a cooler with a built-in compressor, once the power supply is completely stopped,
When one of the loads recovers and restarts, a sequential procedure must be followed, which requires time to return to a steady operating state. Also, unlike the water study lamp, there are no particular conditions for restarting it, but it also takes a considerable amount of time to reach a steady state.

As described above, when one load is being used while the other load is being used, the present invention is capable of supplying power to the other load at a certain ratio without completely stopping the power supply to the other load. The purpose is a power distribution device with

DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described in detail below as illustrated in the accompanying drawings.

1 and 2 show a first diagram of a power distribution device according to the present invention.
The power distribution device includes two power outputs 4.6 branched from one power source 2 in parallel, a triac 8.10, and an arc extinguishing circuit I89 connected in parallel to the triac 8. , energization detector 12, and control circuit 12I14
It is composed of

A power supply circuit 16 is connected to this control circuit 14 for supplying a DC voltage for operation of this circuit. The power supply output 4 is for a load that operates continuously for a long time, and the power supply output 6 is for a load that operates for a short time. Preferably, the power distribution device is a small power distribution device.

The housing may be incorporated into the distribution panel.

The control circuit 14 receives the output of the energization detector 12 which detects the flow of an alternating current, for example, a coil, and includes a detection amplifier 18 which detects and amplifies this energization signal, and a detection amplifier 18 which receives an alternating current voltage from the power source 2. A delay circuit 22 detects this AC voltage (1) and delays the zero-crossing pulse generator pulse by a predetermined time, and a flip-flop circuit receives the outputs of the zero-crossing pulse generator 2o and the delay circuit 22 at reset terminals R and set terminals S, respectively. 24, and 2
It has two resistors 26, 28 and a 3-state buffer 30 that acts as an analog switch.

Assume now that the load connected to the power supply output 4 is operating continuously and the load connected to the power supply output 6 is not being used. Since the energization detector 12 does not detect anything, the detection amplifier 18
The output of is zero. However, the delay IIP1121
22 and 3-stateno (sofa 30 is not operated,
The delay circuit l2I22 continues to give an L level signal -q to the flip-flop 240 set i terminal S, while the output of the 3-state buffer 30 has a high impedance, so a resistor 28 is connected to the terminal d, that is, the gate of the triac lO. Since the DC voltage VCC is applied through the triac 10, the triac 10 is always maintained in an ON state. Furthermore, since the flip-flop 24 is always reset by the zero-cross pulse, its output is always at the H level, and the triac 8 is also maintained in the on state.

Here, when the load connected to the power supply output 6 is used, the energization detector 12 detects energization, and the detection amplifier 18 activates the delay circuit 22 and 3-detail buffer 3.
Sends an enable signal to 0. As a result, the delay circuit 22 transmits the zero-crossing pulse (see FIG. 3 fBI) for a time τ
Simultaneously, the 3-state buffer 30 returns to normal latching operation by supplying the delayed pulse (see FIG. 3 (q1)) to the set terminal S of the 7-lip-flop 240. Figure 3 (F) of the voltage waveform of the power supply 2 shown in the third position is applied to the power supply output 4 by applying the gate signal shown in Figure 3 IDI.
Provides an output with the voltage waveform shown in Similarly, the flip-flop 24 provides the gate signal IEI in FIG. 3 to the triac 10, and supplies the output voltage waveform shown in FIG. 3 to the power supply output 6.

The arc-extinguishing circuit 9 connected in parallel to the triac 8 reduces the voltage waveform of the power source 2 (tAl in FIG. 3) to zero after a delay time τ from the zero-crossing time, that is, turns off the triac 8 and cuts off the power output 4. The operation timing is the delay time Ii! 822 output pulses (
It depends on FIG. 3 (C1).

The delay circuit 22 may be automatically controlled so that the delay time τ is inversely proportional to the magnitude of the energization signal received from the detection amplifier 18, that is, the load current. For example, the settings may be manually set from the outside.

4 and 5 show a second embodiment of the device according to the invention, in which the same elements as in FIGS. 1 and 2 are given the same reference numerals.

According to this second embodiment, an energization detector 12' is also provided on the load side that is continuously used for a long time, and an arc extinguishing circuit 11 is provided in parallel with the triac 10.

The control circuit 11jis14 includes an interlocking switch 32 that can switch any of the power supply outputs 4 and 6 to a load that is used continuously for a long time or a load that is used for a short time, and a detection amplifier 1.
8, and a 3-state buffer 36 controlled by this detection amplifier 34 is newly provided.

The interlock switch 32 is in the illustrated position, ie, 'in'.

When the output 4 is set for a load that is used continuously for a long time and the power supply output 6 is set for a load that is used for a short time, the detection amplifier 34 detects energization and maintains the 3-state buffer 36 in a conductive state. Therefore, its operation is the same as that of the circuit of FIG. That is, when the short-term use load is not used, an H-level gate signal is output from the terminals d and e, and when the short-time use load is used, the terminals d and e are provided with gate signals (D+ and tEl) shown in FIG. The gate signal shown in is output.

Here, if the use of the long-term continuous use load is interrupted, the output of the detection amplifier 34 becomes zero, disabling the 3-state buffer 36, and thus also the delay circuit 12I22 and the 3-state buffer 30. It is disabled, gate output terminals C and d are maintained at H level, and 100% power is supplied to the load used for a short time.

Finally, regarding the trybook, in the first embodiment, the triac 10 switches from the off state to the on state, so it can be of the normal gate turn-on type, but the triac 8 must switch from the on state to the off state. Therefore, a gate turn-off type thyristor can be used. Of course, in this case, the arc extinguishing time FI
69 is disrespectful.

In the second embodiment, these thyristors with different properties can be combined in series, and the properties of each triac can be selectively controlled by a gate signal in conjunction with the interlocking switch 32. Furthermore, as shown in FIG. 6, a phototriac which is not affected by magnetic and electrical interference may be used for the gate trigger.

As described above, according to the present invention, when a large-capacity, short-term use load is used while a large-capacity, long-term continuous use load is being used, the function of the long-term continuous use load is kept to a minimum while the short-term use load is used. It is extremely beneficial that time-use loads can be used at the same time, and even if they are used at the same time, the power consumption can be kept within the contracted power.

[Brief explanation of the drawing]

3 is a voltage waveform diagram of the main part of FIG. 2, FIG. 4 is a configuration diagram showing a second embodiment of the device according to the present invention, FIG. 5 is a detailed diagram of the control circuit of FIG. 4, and FIG. is a diagram showing a phototriac. 2...Power input, 4t6--11L source output, 8.10.
・Triac, 9.11.. Arc extinguishing circuit, 12.. Energization detector, 14.. Control circuit, 16.. Power supply circuit, 18.
・Detection amplifier, 20...Zero cross pulse generator, 22
・・Delay circuit, 24 ・・Flip-flop, 26.28
・Resistor, 30 ・3-state buffer, 32 ・Interlocking switch, 34 ・Detection amplifier, 36 ・3-state buffer (sofa).

Claims (1)

[Claims] Two power supply outputs branched from one power supply, a triac provided in series with the load on each power supply output, an energization detector provided on at least one of the power supply outputs to detect energization to the load, and the triac and a control circuit that controls each of the pulses, and the control circuit includes a zero-crossing pulse generator that detects the zero-crossing of the power supply voltage and generates a pulse, a delay circuit that delays this pulse, and a delay circuit that delays the pulse and the delayed pulse. The pulse receiving circuit includes a flip-flop whose output is connected to the valley gate of the triac, and a circuit that receives the output of the energization detector and operates the delay circuit when energization is detected. A power distribution device that takes special care to control the phase so that the triac on the galvanic output side is energized when there is no load, and is energized alternately with the triac on the other power supply output when there is a load.