JPS58108776A - Junction diode - Google Patents
Junction diodeInfo
- Publication number
- JPS58108776A JPS58108776A JP56206873A JP20687381A JPS58108776A JP S58108776 A JPS58108776 A JP S58108776A JP 56206873 A JP56206873 A JP 56206873A JP 20687381 A JP20687381 A JP 20687381A JP S58108776 A JPS58108776 A JP S58108776A
- Authority
- JP
- Japan
- Prior art keywords
- region
- junction
- diode
- area
- semi
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000758 substrate Substances 0.000 claims abstract description 14
- 239000004065 semiconductor Substances 0.000 claims abstract description 6
- 229910001218 Gallium arsenide Inorganic materials 0.000 abstract description 9
- 238000005468 ion implantation Methods 0.000 abstract description 4
- 238000000034 method Methods 0.000 abstract description 3
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 8
- 230000005669 field effect Effects 0.000 description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 229910052733 gallium Inorganic materials 0.000 description 2
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/8611—Planar PN junction diodes
Abstract
Description
【発明の詳細な説明】
発明の技術分野
ガリウムショット／ゲート電界効果トランジスタ（Ｇａ
、Ａｓ ｔｌＪＥ ８ Ｆ ＥＴ ）と同−基体中に設
けられ、ショットキゲート保護用として特に適するｐ−
ｎ接合ダイオードに関する。DETAILED DESCRIPTION OF THE INVENTION Technical Field of the Invention Gallium shot/gate field effect transistor (Ga
, As tlJE 8 FET) and is provided in the same substrate and is particularly suitable for protecting Schottky gates.
Regarding n-junction diodes.
発明の技術的背景とその問題点
以下ＦＥＴと記載する砒化ガリウムショットキググート
電界効果トランジスタ（ＧａＡ、ｓＭＦ、８ＦｇＴ）
、％に民生用機器に用いるＦＥＴでは、Ｆ Ｅ Ｔのゲ
゛−ト、ソース間にゲートの逆制圧より低い耐圧のｐ−
ｎ接合ダイオードを挿入することにより、ショットキゲ
ートを静電破壊から保障している。この場合ダイオード
の接合面積Ｓ。はダイオードが挿入されたＦＥＴ０高周
波特性をほとんど損わないこと、且つ又必要なゲート保
護性能を有することの二点から決められる。そしてこの
ｐ−ｎ接合ダイオードとしては、（１ａＡｓより安価な
シリコン（Ｓｌ）ダイオードが使用されている。Technical background of the invention and its problems Gallium arsenide Schottkygout field effect transistor (GaA, sMF, 8FgT), hereinafter referred to as FET
,% In FETs used in consumer equipment, there is a p-
By inserting an n-junction diode, the Schottky gate is protected from electrostatic damage. In this case, the junction area S of the diode. is determined from two points: that it hardly impairs the high frequency characteristics of the FET0 in which the diode is inserted, and that it also has the necessary gate protection performance. As this p-n junction diode, a silicon (Sl) diode (which is cheaper than 1aAs) is used.
しかし、Ｓ１ダイオードチツプとＧａＡｓ ＭＥ Ｓ
Ｆ ＥＴテツゾの二個のチップを用いるときには、Ｇａ
ＡｓＭＥＳＦＥＴ−個のチップの場合に比較して、素子
の組立て作業が複雑となり作業性が低下する。However, S1 diode chips and GaAs MES
When using two chips of FET Tetsuzo, Ga
Compared to the case of AsMESFET- chips, the assembly work of the element becomes complicated and the workability decreases.
それ故同−半絶縁性ＧａＡｓ基板上にＦＥＴとゲート保
膿用ｐ−ｎ接合ダイオードを形成することが、作業性を
向上させるうえで望ましい。この要望に沿い半絶縁性基
板ｋ例えばＧａＡｓ Ｙ上に設けたｐ−ｎ接合ダイオー
ドとして、例えば第１図斜視図に示す素子が知られてい
る。この素子はｐ十形領域０υと、このｐ十形領域の側
面に沿い一部（１２は領域内に重ねられ残部０３）は領
域外に分布するｎ影領域とが島状に設けられ、それ散失
々の領域の一部分（１２）を共有する構造をとっている
。Therefore, it is desirable to form an FET and a pn junction diode for gate protection on the same semi-insulating GaAs substrate in order to improve workability. In response to this demand, a device shown in the perspective view of FIG. 1, for example, is known as a pn junction diode provided on a semi-insulating substrate (e.g., GaAs Y). This element has a p-shaped region 0υ and an island-like n-shaded region along the side surface of this p-shaped region (12 overlaps within the region and the rest 03) distributed outside the region. It has a structure in which a part (12) of the scattered area is shared.
一般にＮｐ形領域又はｎ影領域のうちいずれか一方のキ
ャリヤ濃度を他方よシ充分高濃度にして、接合の逆耐圧
が低濃度領域のキャリヤ濃度でほぼ決まるようにし、さ
らにｐ影領域とｎ影領域の夫々の深さについては高濃度
領域の深さＤＨと低濃度領域の深さＤＬについてＤＨ≧
ＤＬとなるように構成している。従って第１図例ではｐ
＋形領領域α１の深さＤＨがｎ形価域（Ｉ３）の深さＤ
Ｌより深くおかれているのである。Generally, the carrier concentration in either the Np type region or the n shadow region is made sufficiently higher than the other so that the reverse breakdown voltage of the junction is approximately determined by the carrier concentration in the low concentration region, and Regarding the respective depths of the regions, the depth DH of the high concentration region and the depth DL of the low concentration region DH≧
It is configured to be DL. Therefore, in the example in Figure 1, p
The depth DH of the +-type region α1 is the depth D of the n-type region (I3)
It is placed deeper than L.
しかしＤＨ≧ＤＬとする場合、第１図で、接合Ｉはｐ十
形領域０１）の−側面の一部でｎ影領域０９との界面に
のみ形成され、との−側面の深さ方向残域並びにｎ影領
域（１３）の底面には形成されない。従って、ダイオー
ドが充分なゲートの保護性能を有するために必要な接合
面積Ｓは、この側面の幅即ち第１図界面の水平辺長さを
Ｗで表わすとき５−ＤＬｘＷにか＼るため、幅Ｗを例え
ばＦ Ｅ Ｔのゲート幅の２倍程度にしなければならな
い。このためダイオードを形成するのに、Ｆ’ＥＴより
も大きい面積を必要とする欠点がある。However, when DH≧DL, in FIG. It is not formed on the bottom surface of the area or the n-shaded area (13). Therefore, the junction area S required for the diode to have sufficient gate protection performance is 5-DLxW, where W is the width of this side surface, that is, the horizontal length of the interface in Figure 1. For example, W must be about twice the gate width of FET. Therefore, there is a drawback that a larger area is required to form a diode than an F'ET.
発明の目的
この発明はこのような欠点を除き、素子占有面積をより
小に得させる接合ダイオードを提供するものである。OBJECTS OF THE INVENTION It is an object of the present invention to provide a junction diode which eliminates the above-mentioned drawbacks and allows the device to occupy a smaller area.
発明の概要
即ちこの発明は（１）半絶縁性半導体基体内に形成され
た一力導電形領域と、この一方４電形領域の側面に沿い
一部は領域内に重ねられ残部は領域外に分布するように
二方導・亀形領域より高濃度に且つ浅く形成された他方
４を影領域との内域を併せ島状に備える接合ダイオード
、又は（２）一方導電形領域の側面から領域内にある他
方導電影領域の重なり距離は、この他方導電影領域の深
さよりも犬である前記（１）項に記載の接合ダイオード
にある。Summary of the Invention Namely, this invention consists of (1) a single-conductivity type region formed within a semi-insulating semiconductor substrate; a portion of the quadriconductivity-type region along the side surface thereof is overlapped within the region, and the remainder is outside the region; A junction diode which has an island shape with the inner region of the other conductive region and the shadow region formed at a higher concentration and shallower than the two-way conductivity type region so as to be distributed, or (2) the region from the side of the one conductivity type region. In the junction diode according to item (1), the overlapping distance of the other conductive shadow region within the junction diode is longer than the depth of the other conductive shadow region.
このようなこの発明の接合ダイオードは、例えばショッ
トキゲート電界効果トランジスタと一体化させるゲート
保護ダイオードに好適する。そしてこのダイオードの特
徴は半絶縁性半導体基体中に深く形成されている一方導
電形領域に対し浅く且つ高濃度の他方導電影領域を共有
領域をおいて設けである点に係る。この場合には接合は
その面積を拡大する。つまり一方導電形領域内に重ねら
れた共有領域の侵入側面と底面とが、接合面積となるか
らである。ゲート保護性能は従来通り確保され、素子の
占有面積をより小さくする。又この場合高濃度領域深さ
ＤＨは、イオン注入法では加速電圧できまる上限が存在
するため、共有領域の重なり距離をＬとしてＬ ＞ Ｄ
Ｉとおくと接合面積を犬に出来る。更に又このダイオー
ドではこのダイオードが降伏時に高濃度領域の底面から
遠去かる空乏層端面を、低濃度領域内にとどめられるよ
うに、それぞれの領域深さＤＨｘ ＤＬを定めるとよい
。Such a junction diode of the present invention is suitable, for example, as a gate protection diode integrated with a Schottky gate field effect transistor. The feature of this diode is that one conductivity type region is formed deeply in a semi-insulating semiconductor substrate, and the other conductivity type region is provided with a shallow, high concentration conductive shadow region with a shared region. In this case the bond expands its area. In other words, the intrusion side surface and the bottom surface of the shared region overlapped in one conductivity type region constitute the bonding area. Gate protection performance is maintained as before, and the area occupied by the device is further reduced. In this case, the high concentration region depth DH has an upper limit determined by the accelerating voltage in the ion implantation method, so L > D, where L is the overlapping distance of the shared region.
By setting it as I, the joint area can be made into a dog. Furthermore, in this diode, each region depth DHxDL is preferably determined so that the end face of the depletion layer, which is far away from the bottom of the high concentration region when the diode breaks down, can be kept within the low concentration region.
発明の実施例
以下この発明の実施例について図面を参照して説明する
。Embodiments of the Invention Below, embodiments of the invention will be described with reference to the drawings.
砒化ガリウムショットキゲート電界効果トランジスタ（
ＧａＡｓＭＥＳＦＨＴ）と同−基体上に設けられるゲー
ト保護用ｐ十ｎ接合ダイオードについて述べる。Gallium arsenide Schottky gate field effect transistor (
A p-n junction diode for gate protection provided on the same substrate as GaAs MESFHT will be described.
に、Ｉ−基板又は１と称する半絶縁性ＧａＡｓ基体（０
）内に選択イオン注入法を用いてｐ十形領域Ｑυ及びｎ
影領域（２３）を、夫々の側面に沿う一部領域（２２１
が共有となるように島状に設けられたものである。又夫
々のキャリヤ濃度はこの例ではＮＡ、＞ＮＤｌ 例え
ばＮ／Ａ：′１ ｘ １０１９／ｃｒ／ｌ 、 ＮＤ’
：： １ ｘ １０１８／ｃｔｆｔで、夫々の深さは高
濃度領域（２１）側のＤＨと低濃度領域（ハ）側のＤＬ
との間でＤＨ＜九であるように、共有部分の重なり距離
りは■、）ＤＨを満足するように構成しである。A semi-insulating GaAs substrate (0
) using selective ion implantation to form p-domain regions Qυ and n
The shadow area (23) is replaced by a partial area (221) along each side.
It was established in the form of an island so that the area was shared. Also, each carrier concentration is NA in this example, >NDl For example, N/A:'1 x 1019/cr/l, ND'
:: 1 x 1018/ctft, each depth is DH on the high concentration region (21) side and DL on the low concentration region (c) side
The overlapping distance of the shared portion is configured to satisfy DH<9, and the overlapping distance of the shared portion satisfies DH.
例えばＬユ３μｍ、 、 ＤＨ’：： ０．１μｍ、
ＤＬ？ ０．３μｍとする。For example, L: 3μm, DH':: 0.1μm,
DL? It is set to 0.3 μm.
このようにすると、接合面は共有領域（２４の低濃度領
域９１ｔｌ側面（２４１）のみならず底面（２４２）に
も形成されるから、接合面積ＳはＷを接合幅とするとき
８ ＝ （Ｌ＋ＤＨ） ＸＷ となる。すでに述べた
ように第１図例構造の場合には８＝ＤＬＸＷであるので
、いまこの値と同じ接合面積を得るだめの接合幅Ｗｘは
、Ｗｘ＝ＷｘＤＬ／（Ｌｏ＋ＤＨ）の関係を用い、Ｌｏ
％ＤＨ％ＤＬに上記の値を代入してＷｘ＝ ０．１ Ｗ
が得られる。従って、ダイオードを形成するのに必要な
面積を従来に比較して１／１０程度に小さくできる。In this way, the bonding surface is formed not only on the side surface (241) of the shared region (low concentration region 91tl of 24) but also on the bottom surface (242), so the bonding area S is 8 = (L+DH) where W is the bonding width. ) Using the relationship, Lo
Substitute the above value for %DH%DL and get Wx = 0.1 W
is obtained. Therefore, the area required to form the diode can be reduced to about 1/10 compared to the conventional one.
同第２図平向図に対し、第４図平面図に示すように接合
幅方向に関して一方導電形領域よりも他方導電影領域を
伸張させてもよい。In contrast to the plan view of FIG. 2, as shown in the plan view of FIG. 4, the other conductive shadow region may be extended more than the one conductivity type region in the junction width direction.
この実施例ダイオードはｐ ＋−ｎ構造であるが、ｎ＋
ｐ構造としてもよろしい。又ｎ−ｐ＋−ｎ。This example diode has a p+-n structure, but an n+
It may also be a p-structure. Also n-p+-n.
ｎ”−ｐ”’ｎ＋・ ｐ十−ｎ−ｐ” ％ ｐ−ｎ＋
−９などの横方向ダイオード素子構造にも適用できる。n"-p"'n+・pten-n-p"% p-n+
It can also be applied to lateral diode element structures such as -9.
第５図及び第６図にｎ−ｐ”−ｎ横方向ダイオード素子
について平面図及び断面図を示す。これ等の両側では高
濃度ｐ＋形領領域２Ｉ）の両側方に共有領域（２２１）
又は（２２２）をおいて低濃度ｎ影領域（２３１）又は
（２３２）をおき、接合（２４１１）、（２４２１）又
は（２４１２）、（２４２２）を形成している。また前
記実施例は同一基板上に設けられるショットキゲート電
界効果トランジスタのゲート保障を目的にしたダイオー
ドであるが、単体のダイオードとしてもよろしい。そし
て半導体基体は砒化ガリウム又この基体内に形成される
各導電影領域は、選択イオン注入法の他エピタキシャル
成長法、熱拡散法あるいはこれらを適当に組合せること
によって形成されてよい。同形成される共有領域が沿う
一方導電形領域側面形状は、平面に限られない。例えば
曲面をなしていてもよい。5 and 6 show a plan view and a cross-sectional view of an n-p"-n lateral diode element. On both sides of these, there are shared regions (221) on both sides of the high concentration p+ type region 2I).
Or (222) is placed and a low density n shadow area (231) or (232) is placed to form a junction (2411), (2421) or (2412), (2422). Furthermore, although the above embodiment is a diode intended to guarantee the gate of a Schottky gate field effect transistor provided on the same substrate, a single diode may also be used. The semiconductor substrate is made of gallium arsenide, and the conductive shadow regions formed within the substrate may be formed by selective ion implantation, epitaxial growth, thermal diffusion, or a suitable combination thereof. The shape of the side surface of the one conductivity type region along which the shared region is formed is not limited to a flat surface. For example, it may have a curved surface.
発明の効果
以上述べたようにこの発明によれば、半絶縁性半導体基
体中に設けられるｐ−ｎ接合ダイオードの接合面積を変
えることなく素子面積を大幅に減少でき、例えばダイオ
ードと同一基板上に設けられるショットキゲート電界効
果トランジスタに接続され、ゲートの保睦に適したダイ
オードを提供できる。Effects of the Invention As described above, according to the present invention, the element area can be significantly reduced without changing the junction area of a pn junction diode provided in a semi-insulating semiconductor substrate. A diode connected to the provided Schottky gate field effect transistor and suitable for gate protection can be provided.
第１図は従来のダイオードに係る斜視図、第２図はこの
発明の実施例ダイオードの平面図、第３図は第２図のＡ
、 −Ａ’線に沿う断面図、第４図は平面外形状を変え
た実施例ダイオード平面図、第５図は他の実施例ダイオ
ード平面図、第６図は同じく断面図である。
第２図乃至第６図で
代理人 弁理士 井 上 −男
第 １ 図
第 ２ 図
第 ３ 図FIG. 1 is a perspective view of a conventional diode, FIG. 2 is a plan view of a diode according to an embodiment of the present invention, and FIG. 3 is a diagram of A in FIG.
, FIG. 4 is a plan view of an example diode with a different out-of-plane shape, FIG. 5 is a plan view of another example diode, and FIG. 6 is a sectional view of the same. In Figures 2 to 6, the agent is Patent Attorney Inoue, Figure 1, Figure 2, Figure 3.
Claims (1)
と、この一方導電形領域の側面に沿い一部は領域内に重
ねられ残部は領域外に分布するように一方導電形領域よ
り高濃度に且つ浅く形成された他方導電影領域との画成
を併せ島状に備えることを特徴とする接合ダイオード ２、一方導電形領域の側面から領域内にある他方導電影
領域の重なり距離は、この他方導電影領域の深さよりも
犬でおることを特徴とする特許請求の範囲第１項に記載
の接合ダイオード[Claims] 1. One conductivity type region formed in a semi-insulating semiconductor substrate; A junction diode 2 characterized in that it has an island shape with a conductive shadow region formed at a higher concentration and shallower than the one conductivity type region, and the other conductive shadow region is located within the region from the side surface of the one conductivity type region. The junction diode according to claim 1, wherein the overlapping distance of the regions is greater than the depth of the other conductive shadow region.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56206873A JPS58108776A (en) | 1981-12-23 | 1981-12-23 | Junction diode |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56206873A JPS58108776A (en) | 1981-12-23 | 1981-12-23 | Junction diode |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS58108776A true JPS58108776A (en) | 1983-06-28 |
Family
ID=16530449
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP56206873A Pending JPS58108776A (en) | 1981-12-23 | 1981-12-23 | Junction diode |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58108776A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6136980A (en) * | 1984-07-18 | 1986-02-21 | ゼネラル・エレクトリック・カンパニイ | Diode |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5221874A (en) * | 1975-08-11 | 1977-02-18 | Hewlett Packard Yokogawa | Group delay measuring device |
| JPS5450277A (en) * | 1977-09-27 | 1979-04-20 | Nec Corp | Semiconductor device |
-
1981
- 1981-12-23 JP JP56206873A patent/JPS58108776A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5221874A (en) * | 1975-08-11 | 1977-02-18 | Hewlett Packard Yokogawa | Group delay measuring device |
| JPS5450277A (en) * | 1977-09-27 | 1979-04-20 | Nec Corp | Semiconductor device |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6136980A (en) * | 1984-07-18 | 1986-02-21 | ゼネラル・エレクトリック・カンパニイ | Diode |
| JPH0578952B2 (en) * | 1984-07-18 | 1993-10-29 | Gen Electric |
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