JPS58108744A - Manufacture of integrated circuit - Google Patents

Manufacture of integrated circuit

Info

Publication number
JPS58108744A
JPS58108744A JP20841781A JP20841781A JPS58108744A JP S58108744 A JPS58108744 A JP S58108744A JP 20841781 A JP20841781 A JP 20841781A JP 20841781 A JP20841781 A JP 20841781A JP S58108744 A JPS58108744 A JP S58108744A
Authority
JP
Japan
Prior art keywords
substrate
resist
high frequency
adhesion
chamber
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP20841781A
Other languages
Japanese (ja)
Inventor
Kougo Tsuboi
坪井 後吾
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP20841781A priority Critical patent/JPS58108744A/en
Publication of JPS58108744A publication Critical patent/JPS58108744A/en
Pending legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G03PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03FPHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/004Photosensitive materials
    • G03F7/09Photosensitive materials characterised by structural details, e.g. supports, auxiliary layers
    • G03F7/11Photosensitive materials characterised by structural details, e.g. supports, auxiliary layers having cover layers or intermediate layers, e.g. subbing layers

Landscapes

  • Engineering & Computer Science (AREA)
  • Architecture (AREA)
  • Structural Engineering (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)

Abstract

PURPOSE:To improve the adhesion of resist to substrate by a method wherein a substrate surface is sputteretched by means of appropriate plasma. CONSTITUTION:A substrate holder 2 fitted with the substrates 1 subject to cleaning process is fixed to a high frequency electrode 3 making the space in chamber 8 vacuum by ordinary means. The gas supply unit 6 supplies the chamber 8 with Ar or O2 gas up to the pressure of 1X10<-4>-1X10<-3> Torr and then the pressure in said chamber 8 is changed to 5X10<-3>-1X10<-1> Torr by means of adjusting the opening of the main valve 7. With this pressure sustained constantly, the high frequency electrode 3 is supplied with high frequency power to produce Ar or O2 plasma. The substrate after cleaning process for 5-10min may be coated with resist without heating and drying process as well as processing interfacial activator.

Description

【発明の詳細な説明】 この発明は集積回路、特に薄膜集積回路の製造方法で、
特に写真製版工程に関するものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention is a method for manufacturing an integrated circuit, particularly a thin film integrated circuit,
In particular, it relates to the photolithography process.

この発明の目的はフォトレジストの基体への密着力を向
上させ、微細なパターンを安定に得ることにある。
The purpose of this invention is to improve the adhesion of photoresist to a substrate and to stably obtain fine patterns.

例えばシブレイ社のAZ系フォトレジストの基体に対す
る密着性は湿度によって大きく影響を受ける。すなわち
基体とレジストの界面に水分が存在すると密着力を著し
く低下させてしまう0従来はレジストを塗布する直前に
基体を乾燥した空気あるいは窒素のようなガス中で10
0〜150°Cに加熱して表面を乾燥させていた。この
方法によって吸着水分のいくらかは除去されてレジスト
の基体に対する密着性は幾分向上する。しかし100〜
150°Cに加熱することは次のようないろいろな好ま
しくない影響を、基体上にすでに形成された薄膜に与え
る1、すなわち、まず処理温度であるが、100〜15
0’Cという温度はすでに基体上に形成された#1摸に
物理化学的な変化をもたらす。このような熱的影響は低
融点金属であるPI)糸ジョセフソン集積回路の製造に
おいて特に顕著に現われる。また、熱処理を一定時間実
施した後、冷却による水分の再吸着を防止するために乾
燥ガス気流中で冷却する必要がある。そして冷却後界面
活性剤による表面処理を必要とし、その後、低湿度のク
リーンルーム内で比較的短時間の間にレジストを塗布し
なければならない。このように熱処理後レジストを塗布
するまでの工程を密着力の低下を避けるために連続した
分単位の時間管理で実施する必要がある。
For example, the adhesion of Sibley's AZ photoresist to a substrate is greatly affected by humidity. In other words, the presence of moisture at the interface between the substrate and resist significantly reduces the adhesion. Conventionally, just before coating the resist, the substrate was immersed in dry air or a gas such as nitrogen for 10 minutes.
The surface was dried by heating at 0 to 150°C. This method removes some of the adsorbed moisture and somewhat improves the adhesion of the resist to the substrate. But 100~
Heating to 150°C has a variety of undesirable effects on the thin film already formed on the substrate, including the following:
A temperature of 0'C brings about physicochemical changes in the #1 pattern already formed on the substrate. Such thermal effects are particularly noticeable in the manufacture of Josephson integrated circuits made of low melting point metals (PI). Further, after heat treatment is performed for a certain period of time, it is necessary to cool the material in a dry gas stream to prevent water from being re-adsorbed by cooling. After cooling, a surface treatment with a surfactant is required, and then a resist must be applied in a relatively short period of time in a clean room with low humidity. In this way, it is necessary to carry out the steps from heat treatment to resist coating in a continuous time-controlled manner on a minute-by-minute basis in order to avoid deterioration of adhesion.

レジストにオーバーハング形状をもたせる必要がないプ
ロセスにおいては、この従来方法で十分な密着力が得ら
れる。しかし、ジョセフソン集積回路のような薄膜集積
回路の製造においてはレジストにオーバーハング形状を
もたせるためにモノクロルベンゼン浸漬処理が必要であ
るが、この処理を行なった場合、レジストの基体に対す
る密着力の影響が従来よシも強調される。すなわち、1
00〜150℃で乾燥のためのベーキングを実施しても
湿度が50チ以上の環境でモノクロルベンゼン浸漬処理
を行なった場合、レジストの剥離が生ずることがある。
In a process that does not require the resist to have an overhang shape, sufficient adhesion can be obtained with this conventional method. However, in the manufacture of thin film integrated circuits such as Josephson integrated circuits, monochlorobenzene immersion treatment is necessary to give the resist an overhang shape, but when this treatment is performed, it affects the adhesion of the resist to the substrate. Traditionally, this is also emphasized. That is, 1
Even if baking is performed for drying at 00 to 150° C., peeling of the resist may occur if the monochlorobenzene immersion treatment is performed in an environment with a humidity of 50° C. or more.

この発明は従来の厳密な注意を払ったプロセス管理が必
要なレジスト塗布工程を簡素化し、かつ従来以上の密着
力を実現しようとするものである。
The present invention aims to simplify the resist coating process, which requires careful process control, and to achieve better adhesion than the conventional resist coating process.

レジストを塗布する前に基体をプラズマ処理装置に設置
し適当なガスのプラズマによって基体表面ラスハラター
エッチする。この浄化処理によってレジストの基体に対
する密着性は著しく向上した。
Before applying the resist, the substrate is placed in a plasma processing apparatus, and the surface of the substrate is subjected to a lath halter etching process using plasma of an appropriate gas. This cleaning treatment significantly improved the adhesion of the resist to the substrate.

またモノクロルベンゼン浸漬苑理を湿度が70多以上の
環境で実施してもレジストの剥離は皆無であった。また
この発明を実施することKよって、従来実施していた乾
燥のだめのベーキングとそれに伴う冷却工程、そして界
面活性剤による表面処理工程が不要となシレジスト塗布
工程が非常に簡素化される。そしてプラズマによる表面
浄化処理後、チャンバーから取り出した後のレジスト塗
布までの時間は特に厳密に管理する必要はない。これは
湿度70%の空中に5時間放置してもレジストの密着性
の低下が見られない事を実験的に確かめた。このように
時間管理が容易である事がこの発明の利点の一つでもあ
る。
Further, even when monochlorobenzene immersion was carried out in an environment with a humidity of 70% or higher, there was no peeling of the resist. Further, by carrying out the present invention, the resist coating process is greatly simplified, since the baking of the drying pot, the accompanying cooling process, and the surface treatment process using a surfactant, which were conventionally performed, are not necessary. There is no need to particularly strictly control the time period from when the surface is purified by plasma to when the resist is applied after being taken out from the chamber. It was experimentally confirmed that no deterioration in the adhesion of the resist was observed even when the resist was left in the air at 70% humidity for 5 hours. One of the advantages of this invention is that time management is easy in this way.

この発明による基体表面のプラズマ浄化処理を実施する
ためには、基体を取り付けることができる高周波電極を
設けた処理装置を使用することが理想的である。高周波
電極に発生する負の直流バイアス電圧を任意に制御でき
るからである。このような装置がない場合には普通の蒸
着装置に放電電極とネオントランスを設置してプラズマ
を得ることができる。との場合、基体の設置場所やプラ
ズマの電位分布は高周波電極を利用した場合と異なり、
かつ制御性に乏しいといった欠点がある。
In order to carry out the plasma purification treatment of the surface of a substrate according to the present invention, it is ideal to use a processing apparatus provided with a high frequency electrode to which the substrate can be attached. This is because the negative DC bias voltage generated at the high frequency electrode can be controlled arbitrarily. If such a device is not available, plasma can be obtained by installing a discharge electrode and a neon transformer in an ordinary vapor deposition device. In this case, the location of the substrate and the potential distribution of the plasma are different from those using high-frequency electrodes.
It also has the disadvantage of poor controllability.

以下に例をあげてこの発明を更に詳細に説明する。図面
において、クリーニング処理を施す基体(1)を装着し
た基体ホルダー(2)を高周波電極(3)に取シ付けて
通常の方法で真空を得る。図面に油回転ポンプ(4)と
油拡散ポンプ(5)を組み合わせた、あシふれた排気系
を使用した真空装置を示す。ガス供給装置(6)からA
rまたは02ガスを1×10−4〜1×1O−3Tor
rの圧力まで導入する。この導入圧力は使用する排気系
の正常動作領域であることが望ましい。次にメインバル
ブ(7)の開度を調節してチャンバー(8)の圧力を5
 X 10−3〜I X 10 ’ Torrにする。
The present invention will be explained in more detail with reference to examples below. In the drawing, a substrate holder (2) on which a substrate (1) to be subjected to cleaning treatment is mounted is attached to a high frequency electrode (3), and a vacuum is obtained in a conventional manner. The drawing shows a vacuum device that uses an exhaust system that combines an oil rotary pump (4) and an oil diffusion pump (5). Gas supply device (6) to A
r or 02 gas at 1×10-4 to 1×1O-3 Tor
Introduce the pressure up to r. It is desirable that this introduction pressure be within the normal operating range of the exhaust system used. Next, adjust the opening degree of the main valve (7) to reduce the pressure in the chamber (8) to 5.
Set to X 10-3 to I X 10' Torr.

この圧力を安定に維持させながら高周波電極(3)に高
周波電力を供給しArまたは02プラズマを発生させる
。この時の高周波電力は1〜2w、そして直流バイアス
電圧は−50〜−100Vである。
While maintaining this pressure stably, high frequency power is supplied to the high frequency electrode (3) to generate Ar or 02 plasma. The high frequency power at this time is 1 to 2 W, and the DC bias voltage is -50 to -100V.

高周波電力を大きくすることは、基体表面の清浄化がさ
らに強められるが、逆に、表面構成物のエツチングによ
る損傷が生じるので望ましくない。
Increasing the high frequency power will further enhance the cleaning of the substrate surface, but this is undesirable since it may damage the surface features due to etching.

5〜10分間のクリーニング処理を終了し、高周波電力
の供給およびガスの導入を停止し、チャンバー内の圧力
を大気圧にして基体を取シ出す。プラズマクリーニング
処理を施した基体は加熱乾燥工程、界面活性剤(例えば
ヘキサメチルジシラザン)の処理工程を経ることなくレ
ジストを密着力のすぐれた状態で塗布することができる
After completing the cleaning process for 5 to 10 minutes, the supply of high frequency power and the introduction of gas are stopped, the pressure in the chamber is brought to atmospheric pressure, and the substrate is taken out. A substrate subjected to plasma cleaning treatment can be coated with a resist with excellent adhesion without undergoing a heating drying process or a surfactant (eg, hexamethyldisilazane) treatment process.

これら2つの工程を省略してもクロルベンゼン浸漬後の
レジストと基体界面での剥離は認められず、プラズマク
リーニング処理がレジストの基体への密着力に多大な効
果を示すことがわかる。このような密着力の向上効果は
SiO薄膜の上にレジスト塗布を実施する場合に特に顕
著に現われる。
Even if these two steps were omitted, no peeling was observed at the interface between the resist and the substrate after immersion in chlorobenzene, indicating that the plasma cleaning treatment has a great effect on the adhesion of the resist to the substrate. This effect of improving adhesion is particularly noticeable when resist is applied on the SiO thin film.

薄膜集積回路の製造においては写真製版工程と主に蒸着
による薄膜形成工程そしてリフトオフ工程のくシかえし
によって積み重ねられてゆくので相互の膜の界面の機械
的、電気的特性に与える影響は無視できない。この発明
によるプラズマクリーニング処理は本来、レジストの密
着力を向上させるものであるが、前段の回路形成のため
のリフトオフによる微少なレジスト残渣を、次段の回路
形成のためのレジスト塗布工程に先立ち、完全に除去す
る効果がある。
In the production of thin film integrated circuits, the layers are stacked by a photolithography process, a thin film formation process mainly by vapor deposition, and a lift-off process, so the influence on the mechanical and electrical properties of the interface between the films cannot be ignored. The plasma cleaning treatment according to the present invention is originally intended to improve the adhesion of the resist, but it is necessary to remove minute resist residues from lift-off for the previous circuit formation prior to the resist coating process for the next circuit formation. It has the effect of completely removing it.

以上のように、この発明を実施することにより次のよう
な利点がある。
As described above, implementing the present invention provides the following advantages.

レジスト密着力向上に伴う集積回路製造プロセスの効率
化と製品の歩留まシの向上ができる。なお、界面活性剤
を使用しなくてもよいので、使用しないことによる積層
薄膜界面の清浄化に伴う電気的特性の安定化が図れるし
、加熱乾燥工程を入れなくてもよいので、入れないこと
によって、集積回路の熱的損傷を少なくすることができ
る。なお又、本発明を実施するには前述したように簡単
な構成機器類でよいから、既存の真空設備あるいはイン
ライン型の自動化製造設備に容易に組み込む事が可能で
ある。
Improved resist adhesion improves the efficiency of the integrated circuit manufacturing process and improves product yield. In addition, since there is no need to use a surfactant, electrical characteristics can be stabilized due to cleaning of the laminated thin film interface by not using it, and there is no need to include a heating drying process, so do not include it. Accordingly, thermal damage to the integrated circuit can be reduced. Furthermore, since the present invention requires simple components as described above, it can be easily incorporated into existing vacuum equipment or in-line automated manufacturing equipment.

【図面の簡単な説明】[Brief explanation of the drawing]

図面は、この発明のプラズマ処理を実施するだめの処理
装置の一例を示す構成図である。 (1) =−基体、(2)−基体ホルダー、(3)−高
周波電極、(4)−・油回転ポンプ、(5)−油拡散ポ
ンプ、(6)−ガス供給装置、(マ)−メインバルブ、
(8)−・チャンバー、(9)−m−直流バイアス電圧
監視装置、(10)−インピーダンス整合器、01)−
高周波電源、(瑞−真空計である。 代理人 葛野信−
The drawing is a configuration diagram showing an example of a processing apparatus for carrying out the plasma processing of the present invention. (1) =-substrate, (2)-substrate holder, (3)-high frequency electrode, (4)--oil rotary pump, (5)-oil diffusion pump, (6)-gas supply device, (ma)- main valve,
(8)-・Chamber, (9)-m-DC bias voltage monitoring device, (10)-impedance matching device, 01)-
High frequency power supply, (Mizu - Vacuum gauge. Agent Makoto Kuzuno)

Claims (1)

【特許請求の範囲】[Claims] パターンの写真製版工程において、基体にフォトレジス
トを塗布する前に基体表面をプラズマ処理することを特
徴とする集積回路の製造方法。
1. A method for manufacturing an integrated circuit, which comprises subjecting the surface of a substrate to plasma treatment before applying photoresist to the substrate in a pattern photolithography process.
JP20841781A 1981-12-23 1981-12-23 Manufacture of integrated circuit Pending JPS58108744A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP20841781A JPS58108744A (en) 1981-12-23 1981-12-23 Manufacture of integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP20841781A JPS58108744A (en) 1981-12-23 1981-12-23 Manufacture of integrated circuit

Publications (1)

Publication Number Publication Date
JPS58108744A true JPS58108744A (en) 1983-06-28

Family

ID=16555883

Family Applications (1)

Application Number Title Priority Date Filing Date
JP20841781A Pending JPS58108744A (en) 1981-12-23 1981-12-23 Manufacture of integrated circuit

Country Status (1)

Country Link
JP (1) JPS58108744A (en)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0208618A2 (en) * 1985-07-09 1987-01-14 Shin-Etsu Chemical Co., Ltd. A mesh and printing screen for screen printing and a method for the preparation thereof
EP0220121A2 (en) * 1985-10-14 1987-04-29 Shin-Etsu Chemical Co., Ltd. A method for the preparation of a screen mesh for screen printing
US5372677A (en) * 1991-12-18 1994-12-13 Kawasaki Steel Corporation Method of manufacturing semiconductor devices
US8056257B2 (en) * 2006-11-21 2011-11-15 Tokyo Electron Limited Substrate processing apparatus and substrate processing method
JP2023093567A (en) * 2020-07-07 2023-07-04 ラム リサーチ コーポレーション Integrated dry processes for patterning radiation photoresist patterning
US11921427B2 (en) 2018-11-14 2024-03-05 Lam Research Corporation Methods for making hard masks useful in next-generation lithography
US11988965B2 (en) 2020-01-15 2024-05-21 Lam Research Corporation Underlayer for photoresist adhesion and dose reduction

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0208618A2 (en) * 1985-07-09 1987-01-14 Shin-Etsu Chemical Co., Ltd. A mesh and printing screen for screen printing and a method for the preparation thereof
EP0220121A2 (en) * 1985-10-14 1987-04-29 Shin-Etsu Chemical Co., Ltd. A method for the preparation of a screen mesh for screen printing
US5372677A (en) * 1991-12-18 1994-12-13 Kawasaki Steel Corporation Method of manufacturing semiconductor devices
US8056257B2 (en) * 2006-11-21 2011-11-15 Tokyo Electron Limited Substrate processing apparatus and substrate processing method
US11921427B2 (en) 2018-11-14 2024-03-05 Lam Research Corporation Methods for making hard masks useful in next-generation lithography
US11988965B2 (en) 2020-01-15 2024-05-21 Lam Research Corporation Underlayer for photoresist adhesion and dose reduction
JP2023093567A (en) * 2020-07-07 2023-07-04 ラム リサーチ コーポレーション Integrated dry processes for patterning radiation photoresist patterning

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