JPS5810856A - Manufacture of complementary type semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To decrease the leaking current at a junction part by opening contact holes on the side of a well regions, introducing impurities through said holes, opening contact holes on the substrate side, introducing impurities, and forming a deep P-N junction. CONSTITUTION:N type second semiconductor layers 13a and 13b are formed on a P well 12 in the substrate 11. P type first semiconductor layers 14a and 14b are formed on a substrate 11 and an insulating layer 16 is deposited. The contact holes 8 reaching layers 13a and 13b are opened through a resist film 17 and a photomask 18. The N type impurities are introduced in a self-aligning mode. The P-N junctions is formed in the deep part and the leaking current is decreased. Then the contact holes are likewise opened in the layers 14a and 14b, and the complementary type semiconddetor device, wherein the leaking current at the junction part is decreased, is obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of manufacturing a complementary semiconductor integrated circuit device.

In recent years, the development of semiconductor integrated circuit devices has been remarkable.
In particular, complementary semiconductor integrated circuit devices have achieved remarkable development due to their low power consumption and wide power supply operating range. However, as patterns become finer in conventional manufacturing methods, weaknesses not seen in other devices have been exposed.

That is, FIG. 5g1 is a cross-sectional view of a complementary semiconductor device at the time of forming a contact hole by the conventional method.

In the figure, a P-type semiconductor layer 2 (hereinafter referred to as P-type well) is formed on one surface side of an N-type semiconductor substrate 1, and N-type source and drain regions 3a, 3bt, N
P-type source and drain regions 4a and 4b are formed on the type substrate 1.
A contact hole 8 is formed in the insulating layer 6 using the photoresist film 7 as a mask material.Normally, the process of forming this contact hole 8 is performed using an N-type semiconductor. Since the process is performed simultaneously on both the source and drain regions 3a and 3b of the P-type semiconductor layer and the source and drain regions 4a and 4b of the P-type semiconductor layer, for example, it is performed to reduce junction leakage current of a normal N-type semiconductor layer. If an attempt is made to diffuse phosphorus from the contact opening, a 4CP-N junction will be formed in the P-type semiconductor layer.

Conversely, if similar measures are taken for the P-type semiconductor layer, a PN junction is formed in the N-type semiconductor layer, making it extremely difficult to reduce the junction leakage current.

An object of the present invention is to provide an entire method for manufacturing a complementary semiconductor integrated circuit device that can eliminate this difficulty and reduce leakage current at the junction of both the P-type semiconductor layer and the N-type semiconductor layer.

Next, the present invention will be explained using examples.

FIG. 2 (al to f) is a sectional view for explaining the manufacturing process of an embodiment of the present invention. First, Figure 2(a)
A P-type well 12 is entirely formed on one surface of an N-type semiconductor substrate 11, and an N-type second semiconductor layer 13a, 13b- is formed in the P-well 12 as a source and drain region of a MOS transistor on the surface side thereof. Then, P-type layer 1 semiconductor layers 14a and 14b are provided on the substrate 11, an insulating layer 16 of gold is deposited to cover them, and a photoresist film 17t-insulating layer 1 is formed.
FIG. 6 is a cross-sectional view at a step of layering on top of No. 6; This photoresist film 17 is partially exposed using a conventional photomask 18 to determine a pattern when forming contact holes connecting the N-type second semiconductor layers 13a, 13b and external wiring metal. It becomes an etching-resistant film.

In this example, a so-called negative type 7 was used, in which the exposed part remains and the unexposed part dissolves in the developer.
A photoresist film may be used, or a positive photoresist film may be used by reversing the brightness of the photomask. As an etching-resistant film for pattern determination of the photoresist film 17t, an N-type second semiconductor layer 13a,
Contact hole 8t reaching 13b - the open state is the second
It is figure (b). At this time, the P-type first semiconductor layer tj”a
, i4b remain covered with the insulating layer 16. Next, the N14 second semiconductor layer 1 is removed.
N-type impurities are introduced in a self-aligned manner through contact holes 8 reaching 3a and 13b. The introduction method is the diffusion method,
Due to the ion implantation method, phosphorus is suitable as the N-type impurity, but arsenic may also be used. At this time, the insulating layer 16
Therefore, no N-type impurity is introduced into the P-type semiconductor layers 14a and 14b. This state is shown in Figure 2 (C). By introducing this self-aligned N-type impurity, the contact hole 8
Through N-type second semiconductor layer 13a, 13b'ft: When connected to external wiring metal, N-type second semiconductor layer 13a.

13b and the Pit well 12, the leakage current at the 6PN junction can be completely reduced. This is because the PN junction at the opening of the contact hole is formed at a deeper portion than in the past, making it difficult for external wiring metal to penetrate into the PN junction.

Next, a photoresist film 20 is deposited again, and a photomask 19 is shown in FIG. ). Next, using the photoresist film 20 as an etching-resistant film for pattern determination, a contact hole 9f reaching the P-type layer 1 semiconductor layer 14a, 14b is opened as shown in FIG. 2(e). . In the state shown in FIG. 2(e), P-type impurities are introduced in a self-aligned manner by ion implantation using the photoresist film 20 as a mask, and then the photoresist film 20 is removed.
Figure 2 shows the state in which the impurities introduced into the contact hole are activated by high-temperature heat treatment.

Boron is desirable as the P-type impurity. A complementary semiconductor integrated circuit device is completed by covering the state shown in FIG. 2 with metal for external wiring and forming a pattern.

As described above, according to the present invention, the N-type second semiconductor layer 13g
, 13b to the P-well 12 and the leakage current from the pH first semiconductor layers 14a, 14b to the N-type semiconductor substrate 11 are reduced. We can overcome this problem and solidify our superiority.

In the table, in Example 91, N type is one conductivity type, l! Although t' corresponds to the opposite conductivity type, the present invention can of course also be applied to the opposite conductivity type. Further, although the P-type well is formed on the N-type semiconductor substrate, it goes without saying that forming an N-type well on the P-type semiconductor substrate also falls within the embodiments of the present invention.

[Brief explanation of the drawing]

FIG. 1 is a sectional view of an intermediate step according to a conventional method, and FIGS. 2(a) to 2) are sectional views of each step of an embodiment according to the present invention. 1.11...N-type semiconductor substrate, 2,12...
...P-type well, 3 a, 3 b, 13 a
, 13b---N-type second semiconductor layer, 4a
, 4 b, 14 a, 14 b---
-P type @1 semiconductor layer, 5.15...MOS) transistor gate electrode, 6.16...insulating layer,
7,17゜20...Photoresist ill, 1
8.19...Photomask. or]

Claims (1)

[Claims] A step of forming a well region of an opposite conductivity type on a part of the whole surface side of a semiconductor substrate of one conductivity type, and a source/drain region of a first M08) transistor on the whole surface side of the semiconductor substrate outside the well region. a step of forming a first semiconductor layer of opposite conductivity type as zMO8) in the well region;
A step of forming a second semiconductor layer of one conductivity type as a source/drain region of the @1 semiconductor layer and an external wiring metal on an insulating film covering the whole surface side of the semiconductor substrate. - fully opening a part of the contact hole @1 for connection or a second contact hole for connecting the second semiconductor layer and external wiring metal to the insulating film; A step of introducing an impurity atom that causes the same conductivity type into the semiconductor layer that this contact hole communicates with through this contact hole, and then forming the other contact holes i-g in the insulating film and passing the contact hole through this contact hole. 1. A method for manufacturing a complementary semiconductor integrated circuit device, comprising the step of introducing impurity atoms of the same conductivity type into semiconductor layers that communicate with each other.