JPS58107739A - Alarm detecting circuit - Google Patents

Abstract

PURPOSE:To produce an alarm for only a failure of a low-order group device system without producing an alarm for a failure of a high-order group device system, by storing an AIS signal in a storage device. CONSTITUTION:When the AIS signal is transmitted at the failure of the high- order group device system, this signal is detected by an AIS detection circuit 9 and a signal of ''1'' level is outputted. A synchronism failure and input interruption detecting circuit 8 detects out-of-synchronism or interruption of input signal, and a signal of level ''1'' is outputted. A storage device 12 is set at a rising part (0 level to 1 level) of a signal from the circuit 9, the output of the circuit 8 is inhibited at an AND gate 13, and no alarm output produces in case of the failure of the high-order group device system.

Description

Detailed Description of the Invention (a) Technical Field of the Invention When a failure occurs in a high-order group multiplexing device (hereinafter referred to as a high-order group device) system, the process from a high-order group multiplexing device to a low-order group multiplexing device f (hereinafter referred to as a low-order group device) The present invention relates to an alarm detection circuit that receives an alarm signal to notify a person, and relates to an alarm detection circuit that outputs an alarm only when a low-order group device has a failure.

In recent years, in the field of digital communications, in order to make digital transmission paths more economical, various multiplex converters have been used to construct digital communication networks, and maintenance of these digital communication networks has also become necessary. Therefore, there is a demand for easier maintenance of digital communication networks.

(c) Prior art and problems A conventional alarm power circuit will be explained using FIGS. 1 to 3.

FIG. 1 is a configuration diagram of a digital communication network.

In the figure, 1.2.5.6 is a low-order group device, and 3.4 FIG. 2 is a configuration diagram of a conventional alarm detection circuit.

In the figure, 7 is a signal input terminal (hereinafter referred to as an input terminal), 8 is a synchronization failure and input disconnection detection circuit, 9 is an AIS signal detection circuit, 10 is a Nant gate, and 11 is an alarm output terminal (hereinafter referred to as an output terminal).

Figure 3 shows operation #5 in Figure 2! -Illustration. In the figure, (a) to (d) are signals from points 2 to 0 in FIG. 2, respectively.

Possible failures in the digital communication network shown in FIG. 1 include failures in the high-order group devices 3 and 4 systems and failures in the low-order group devices 1, 2, 5, and 6 systems. Now, if there is a problem with either the higher-order group device 3.4 system or the lower-order group device 1.2.5.6 system, the lower-order group device 1.2.5.6 is normally used. It is possible to determine that there has been a failure because the input of the digital signal is lost, but the high-order group devices 3 and 4 systems or the low-order group device 1.

I don't know which system (2, 5, or 6) is causing the problem. Therefore, it is necessary to investigate which fault is occurring, but this takes a great deal of time.

For this reason, conventionally, in the case of a failure in a high-order group device system, the high-order group device sends a signal with a unique pattern (for example, all "1s") called an AIS signal to the low-order group device. It informed me that there was a problem with the higher-order group system.

A circuit for receiving this AIS signal is shown in FIG. This is an F alarm detection circuit. Here, the alarm detection shown in Figure 2 is shown in Figure 3 (a).
) is a normal digital signal t t up to ta
a”-tb is the AIS signal g, tb”ta is the input signal disconnection state for troubleshooting the higher-order group equipment, and ta is
This is the digital signal after the normal state has been restored. When the signal shown in Fig. 3 (a) K is input from the long terminal 7, A
The IS detection circuit 9 detects only the AIS signal, during which it outputs an 11'' level signal as shown in FIG. When the input signal is cut off due to a synchronization failure such as loss of synchronization of the low-order group device due to a failure or repair of a failure in the high-order group device, the @l” level signal is output as shown in Fig. 3(e). Output. The outputs of the AI8 detection circuit 9 and the synchronization failure and input disconnection detection circuit 8 are
After inputting 0 and taking NAND, the output shown in FIG. 3(d) appears at the output terminal 11. In other words, in the alarm detection circuit, when an AIS signal is received, the fault is in the higher-order equipment system, and there is no need for maintenance, so the alarm is prohibited to notify the maintenance personnel. However, such conventional alarm detection circuits This configuration has the following drawbacks. That is, this alarm detection circuit issues an alarm when there is a fault in the lower order group transmission line and the input signal to the alarm detection circuit is cut off, but as is clear from FIG. An alarm is also issued when equipment system failures are recovered. Therefore, in the case of a failure in the higher-order group device system, the higher-order group device must notify the maintenance personnel of the lower-order group device. That is, in the case of a failure in the high-order group device system, there is a drawback that the high-order group device must output one AI8 signal to the low-order group device to notify that there is a failure in the high-order group device system.

(d) Object of the Invention The present invention eliminates such conventional drawbacks and provides the following advantages:
To facilitate the maintenance of digital signals by providing an alarm detection circuit which can notify that there is a failure in a high-order group equipment system by simply sending an AIS signal, and which issues an alarm only when there is a failure in a lower-order group equipment system. 0 for the purpose.

(・) Structure of the invention Provided in a low-order group multiplex converter connected via a high-order group multiplex converter, when there is a failure in the high-order group multiplex converter system, the high-order group multiplex converter system In an alarm detection circuit that receives an alarm signal to be notified to the low-order group multiplex converter, a storage means is set when the alarm signal is received, and is reset at 9 o'clock when synchronization is established in the low-order group multiplex converter. (f) Embodiment of the Invention Using FIGS. 4 to 6, the present invention will be described. The alarm detection circuit will be explained.

FIG. 4 is a block diagram of the alarm detection circuit of the present invention. In FIG. 0, the same numbers as in FIG. 2 indicate the same circuits. Also,
12 is a storage device, and 13 is an AND gate.

5 and 6 are explanatory diagrams of the operation of FIG. 4.

In the figure, (a) to (.) are signals at points 9 and 0 of the 4th Fm, respectively.

First, a case where an AIS signal is sent out from a higher-order group device will be explained using FIGS. 4 and 5.

The signals shown in FIG. 5(a) are normal digital signals up to ta @ ta-tb are AIS signals s tb-ta
is an input signal disconnection state yt for fault repair of higher-order group equipment
This is the digital signal after the normal state has been restored from e. When the signal shown in FIG. 5(a)K is input from the input terminal 7, the AIS detection circuit 9 detects only the AIS signal, as explained in the conventional example, and during that time, as shown in FIG. 5(b), A signal of "L" level is output to.

In addition, the synchronization failure and input disconnection detection circuit 8 detects when the input signal is disconnected due to a synchronization failure such as loss of synchronization of the low-order group device due to a failure in the high-order group device system, or when a failure in the high-order group device is repaired. , while the input signal is cut off due to a failure in the low-order group device system, a signal of @l'' level is output as shown in FIG.

The output of the synchronization failure and input disconnection detection circuit 8 is the reset side of the storage device 12 and the ant game fK large input, and the output of the AIS detection circuit 9 is the memory superimposition and the output of the AI8 detection circuit 9 is the memory It is input to the set side of the device 112. This storage device 12 is set at the rising edge of the signal from the A'IS detection circuit 9 to the ``Om0m level l'' level, and the signal from the synchronization failure and input disconnection detection circuit 8 is set to ``''. 11 level It is reset at the fall to the "0" level. That is, the storage device 12
It is set at ta shown in the figure and reset at to. Therefore, between ta and t, the memory device 12 is set, and the output of the memory device 12 becomes 0 as shown in FIG.
As shown in e), it becomes @0 level. In other words, in the case of a failure in the high-order group equipment system, there will be no alarm output.Next, using Figs. The signal shown in Figure 6 (&) is a normal digital signal up to t, and from t onwards, the input signal is interrupted due to a failure in the low-order group digital transmission M. It is in good condition.

When the signal shown in FIG. 6(a) is input to the input terminal 7, the AIS detection circuit 9 cannot detect the AIS detection signal, so the output is "θ" as shown in FIG. ``Pal Naru. In addition, the synchronization failure and input disconnection detection circuit 8
Then, since the input signal is cut off at time t in FIG. 6, from this point on, as shown in FIG. 6(C), the ``ll'' level is output. At this time, the storage device 12 does not receive the ζ1-level signal from the AIS detection circuit 9, so it is not set and does not store the output of the synchronization failure and input disconnection detection circuit 8. Therefore, the output of the storage device 12 is θ) in FIG.
As shown in FIG. 6(e), since the output of the synchronization failure and input disconnection detection circuit 8 is output as is, the output terminal 11 receives an alarm output from the moment the input signal is disconnected, as shown in FIG. 6(e). is obtained.

In other words, the alarm detection circuit of the present invention can output an alarm only when there is a failure in the low-order group device system. (0) Effects of the Invention According to the present invention, the alarm can be output only when there is a failure in the low-order group device system. Since it is possible to realize an alarm detection circuit that can
In the case of a failure in the higher-order group device system, there is no need to contact the lower-order group device from the higher-order group device, making maintenance of the digital communication network easier.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of a digital communication network, Fig. 2 is a block diagram of a conventional alarm detection circuit, Fig. 3 is an explanatory diagram of the operation of Fig. 2, and Fig. 4 is a diagram of the alarm detection circuit of the present invention. Configuration diagram, Figure 5,
FIG. 6 is an explanatory diagram of the operation of FIG. 4. In the figure, 1.2.5.6 is a low-order group device, 3. ``4 is the next group device, 7 is the signal input terminal, 8 is the synchronization failure and input disconnection detection circuit, 9 is the AIS signal detection circuit, 10 is the Nando game)
, 11 is an alarm output terminal, 12 is a storage device, 13 is an AND gate, 2. is a higher order group digital transmission line, 21 to 2.
is a low-order group digital transmission path.

Claims (1)

[Claims] Provided in a low-order group multiplex converter connected via a high-order group multiplex converter, when there is a failure in the high-order group multiplex converter system, the high-order group multiplex converter transmits a message to the low-order group multiplex converter. An alarm detecting circuit that receives an alarm signal to notify the user of the alarm, further comprising a storage means that is set when the alarm signal is received and reset when synchronization is established in the low-order group multiplex converter. Detection circuit 0