JPS5810710B2 - Time scale display - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention comprises a signal generator for generating clock pulses having a predetermined pulse time interval, a divider circuit responsive to the clock pulses to generate a pulsed reference signal, and a divider circuit responsive to a test signal. a detection circuit for generating a test reference signal representative of a first phase portion of the test signal; and an output responsive to a predetermined change in state of the pulsed reference signal and a change in state of the test reference signal representative of a time interval therebetween. and a first bistable switching element for generating a signal.

For example, in order to maintain telephone trunk lines and other communication systems, various measurements of system characteristics are performed.

Important among these is the measurement of group delay in telephone relay systems.

Group delay is the delay between passing a test signal through the system under test, such as a telephone trunk, and then the occurrence of a given phase position of the received test signal and the transmitted or reference pulse signal. Determined by measuring time intervals.

One such group delay measurement scheme is described in U.S. Pat.

In this scheme, the time interval between the occurrence of a received test signal and a transmitted or reference pulse signal is measured by using bistable switching elements.

The bistable element switches from a first stable state to a second stable state and then back to the first stable state in response to a received or test signal and a transmitted or reference signal.

In such a system, more accurate time interval measurements are made by adjusting the bistable element to exhibit only time intervals that are less than or equal to the time interval between adjacent reference pulses.

This is conventionally accomplished by using a gate circuit that is controlled to selectively inhibit the reference pulse from being applied to the bistable element.

The signal controlling the gate circuit is generated by a monostable multi-by-break with an adjustable unstable time interval giving a known time interval range.

This monostable multi-bi break is then triggered by a pulse signal with a period equal to the test signal period.

This period is also an integer multiple of the spacing between adjacent reference pulses.

This prior art measurement scheme involves manually adjusting the instability time interval of the monostable multibibreak to vary the time given to the bistable element to effectuate the desired switching of the reference pulse.

The output of this bistable element is then displayed on a meter, where the group delay time interval is displayed as the sum of the range indicated by the meter reading and the manual adjustment of the monostable multibibreak.

Conventional methods provide satisfactory measurements of group delay but require human intervention to adjust the system to obtain the correct measurement range.

It is undesirable to require the use of a human operator to perform delay measurements.

Indeed, in order to meet the maintenance demands of today's telephone systems, some, if not all, testing procedures must be fully automated, thus requiring minimal human intervention. must be done.

Other problems exist with such automatic time interval range setting schemes.

This becomes a problem when the remaining time interval to be measured is almost zero, or when a predetermined change in the state of the reference signal occurs between clock pulses.

In such instances, the signals used to set and reset the bistable switch element will be applied to it at unscheduled times, thereby creating an uncertain condition.

For example, a reset signal may be applied before a set signal.

In this case the bistable element is not switched correctly.

This causes a continuous periodic operation in conventional autoranging schemes, which causes errors in time interval measurements, if any at all.

The above-mentioned problem is solved according to the present invention by selectively varying the pulse width of one of the pulses of the pulsed reference signal in response to the output of the first bistable switch element and the clock pulse. a first control circuit for causing the width of the pulse time intervals of the output of the element to vary within a predetermined time interval (i.e., set and reset during one clock pulse time interval); The present invention is solved by providing an automatic scale range setting device using a time interval measurement method.

Further, in a second embodiment of the present invention, the pulse width of the test signal is selectively changed in response to a predetermined output of the first bistable switching element, whereby the pulse reference signal and the test signal are The invention is characterized in that it includes a second control circuit that eliminates uncertainty in the automatic time interval range setting by causing the bistable switch elements to be applied with a predetermined pulse time relationship.

In accordance with the present invention, the time interval measurement scheme achieves automatic time ranging by selectively controlling the time of the pulsed reference signal with respect to the test signal.

This is accomplished by selectively varying the pulse time interval of one or several pulses of the reference signal.

More specifically, the time interval measurement method according to the invention is
It includes a clock pulse source that is applied to the divider circuit to generate a pulsed reference signal.

The pulsed reference signal typically has a period equal to an integer multiple of the time interval between adjacent clock pulses.

This pulsed reference signal is supplied to a bistable switching element,
The bistable switching element is switched from a first stable state to a second stable state in response to a predetermined change in the state of the reference signal.

A signal representative of the predetermined position of the received test signal is also provided to the bistable element, thereby returning the bistable element from the second stable state to the first stable state.

According to the invention, automatic time ranging prohibits this bistable element from supplying the divider circuit with a number of clock pulses equal to the number of clock pulses that occur during the time interval in the second stable state. It is executed by

Therefore, the relative time of the reference pulse signal is changed by extending one or several cycles.

This lengthened one cycle or several cycles of the reference signal then causes a delay in switching the bistable element from the first stable state to the second stable state.

The function of this circuit is to switch the bistable element from a first stable state to a second stable state and also within a time interval of a clock pulse adjacent to the first stable state.

The operations of the present invention that accomplish this purpose are commonly referred to as "autoranging."

Once autoranging has taken place, the number of inhibited clock pulses is counted and the time intervals represented by these clock pulses are combined with the time intervals during which the bistable element is in its second stable state. This provides the desired accurate time measurement.

In order to conveniently count the forbidden clock pulses and to minimize errors caused by noise or other transient signals, according to another feature of the invention, the reference pulses are counted until the required number is reached. Only one clock pulse is inhibited during each cycle of the signal.

According to the invention, automatic time spacing is therefore carried out by varying the pulse widths of successive reference pulse signals by unit increments until the required time relationship between the reference pulse test signals is achieved.

According to one embodiment of the invention, the test signal is shifted by selectively varying the width of a pulse signal representing a predetermined reference position of the test signal.

As mentioned earlier, when the autoranging scheme is in an indeterminate state, the bistable element switches to a second bistable state for a period that exceeds the known time interval between each autoranging cycle. be done.

Therefore, the shifting of the test signal is controlled by detecting the output signal generated by the bistable switching element.

During a plurality of autoranging cycles, when the bistable element is in the second stable state for more than a predetermined time interval, the test signal is shifted by an increment less than the time interval of adjacent clock pulses.

By shifting the test signal, the uncertainty region is removed and accurate time intervals are measured.

FIG. 1 is a simplified block diagram of a delay time interval measuring circuit according to the present invention.

2 and 3 show waveform diagrams of signals generated in the circuit shown in FIG. 1. FIG.

The waveforms in FIG. 2 illustrate the operation of the present invention when measuring a test signal that lags behind a reference signal.

The waveforms in FIG. 3 illustrate the operation of the present invention in measuring a test signal leading a quasi-signal.

The waveforms shown in both FIG. 2 and FIG. 3 are named to correspond to the points in the circuit shown in FIG.

Referring to FIG. 1, a pulse generator 101 generates a pulse signal with a predetermined stable time interval selected to achieve the desired accuracy for measuring delay time intervals.

Waveform A shown in FIG. 2 represents the clock pulse signal generated at the output of pulse generator 101. Waveform A shown in FIG.

To achieve high accuracy of time interval measurements, the generator 10
The width of each pulse generated at one output must be minimized.

However, the pulse width must not be so narrow that it cannot work with other circuit components utilized to implement the invention.

For example, flip-flops and other circuit elements cannot respond to pulses with extremely narrow pulse widths.

A narrow pulse signal with an acceptable width is used as a clock 102.
is generated by applying a signal from 1 to a narrow pulse generator 103.

The frequency of the clock signal is selected to obtain the desired time spacing between pulses.

Details of the narrow pulse generator 103 are shown in FIG.

Referring to FIG. 4, details of narrow pulse generator 103 are shown.

The operation of pulse generator 103 is simple and relies primarily on the inherent signal delays of logic circuits.

For example, symmetrical pulse signals generated by clock 102 (FIG. 1) are applied to the input of inverter 401 and the input of AND gate t-402.

As is well known to those skilled in the art, the output of inverter 401 is normally at a high level, and AND gate 402 responds to a high level at its output when both of its inputs are provided with a high level signal at the same time. Generates a status signal.

Therefore, at the moment when the clock signal is applied to the inverter 401, one input of the AND gate 402 is at the "high" level, and the output of the AND gate 402 is also at the "high" level state.

Inverter 401 switches to a ``low'' state in response to a change in the state of the clock pulse after a time interval equal to the internal delay of inverter 401 has expired.

Typically this delay is about 10 nanoseconds.

AND gate 402 then switches to a low state in response to the change in state of the signal developed at the output of inverter 401.

Therefore, the pulse signal generated at the output of AND gate 402 has a width equal to the internal delay time interval of inverter 401.

The internal delay of AND gate 402 merely delays its output pulse and does not contribute to the width of the output pulse.

The width of the pulses generated by narrow pulse generator 103 is increased as required by using capacitor 403.

Typically, pulses with a width of 30 nanoseconds are desired.

Therefore, the value of capacitor 403 is selected to provide an additional 20 nanosecond delay.

Returning to FIG. 1, the output of pulse generator 101, shown as waveform A in FIG. 2, is applied to one input of AND gate 105 and to controllable gate 104.

Gate 104 may be any of a variety of controllable switching devices known to those skilled in the art.

Advantageously, gate 104 is a logic gate with an inhibit input.

Gate 104 is normally energized to provide the pulse signal output of generator 101 to divider 106 .

Divider 106 generates a pulse signal with a period equal to an integer multiple of the time interval between pulses provided by generator 101.

In this example, although this in no way limits the scope of the invention, divider 106 performs a 4:1 division in response to the clock pulse shown in waveform A of FIG.
A signal as shown by the dotted line in waveform B in the figure is normally generated.

The solid line signal of waveform B in FIG. 2 represents the output of divider 106 when autoranging is performed in accordance with the present invention, as will be discussed below.

The signal generated at the output of divider 106 is sent to trigger circuit 10.
7 is given.

Trigger circuit 107 generates a pulse signal as shown in waveform C of FIG. 2 in response to a positive change in the output signal of divider 106.

Again, the signal represented by the dotted line in waveform C of FIG. 2 represents the signal that would be generated if autoranging was not performed.

The signal shown by the solid line of waveform C in FIG. 2 shows the operation of trigger 107 when automatic range setting is performed.

The pulse signal generated by the trigger 107 is applied to the set inputs of a zero phase flip-flop 110 and a 180 degree flip-flop 111.

Flip-flops 110 and 111 are both trigger 1
07 to switch from a low level state to a high level state, producing signals at their respective outputs as shown by waveforms E and K in FIG. 2, respectively.

The received test signal to be measured is provided to zero-crossing detector 120 via input terminal 115.

Detector 120 responds to the applied test signal by generating a pulse signal at point 121 representing the location of the zero crossing in a positive transition of the test signal as shown in the waveform of FIG.

Detector 120 also generates a pulse signal at point 122 representing the location of the negative going zero crossing of the test signal, as shown in waveform J of FIG.

That is, detector 120 generates signals representative of the zero phase position and the 180° phase position of the received test signal.

A pulse signal representing the zero phase position of the test signal as shown in the waveform of FIG.
supplied to the reset input of

This switches flip-flop 110 from a high state to a low state, which is shown in waveform E of FIG.

The pulse width of the output signal produced by flip-flop 110 is adjusted to fall within the time interval between adjacent pulses produced by pulse generator 101 in accordance with the present invention.

As stated above, the operation of the present invention that achieves this objective is referred to as "autoranging."

The output of flip-flop 110 is provided to a second input of AND gate 105.

The operation of AND gate 105 is simple.

Gate 105 allows clock pulses to pass only when the output of flip-flop 110 is in a high level state.

These clock pulses generate a monostable multi-by-break 123 as shown in waveform F in FIG.
and is supplied to the utilization means 124.

In the utilization means 124, the pulses are fed by an AND gate 105 to a counter 130, where they are stored until needed.

Since a 4:1 division is used in this example, counter 130 only needs to be capable of counting seven pulses.

This represents the maximum number of pulses that will be "gated out" during an autoranging cycle.

The operation of the counter 130 will be explained in detail later.

Monostable multi-bi break 123 is AND gate 105
A pulse signal having a predetermined time interval is generated in response to a clock pulse appearing at the output of the circuit.

In this example, the interval between the pulse signals generated by the monostable multi-bi break 123 is equal to one-half of the clock pulse time interval, as shown in waveform G of FIG.

The monostable multi-by break 125 responds to the negative change in the output signal produced by the mono-stable multi-by break 123, as shown in waveform H of FIG. Generate pulse signals with small time intervals.

The total period of the output signal produced by the monostable multi-bibreak 125 is equal to NT.

where N is the number of pulses appearing at the output of AND gate 105 and T is the time interval between adjacent clock pulses.

However, the time intervals of the individual control signals generated by monostable multibi breaks 123 and 125 can be adjusted to any particular It is not necessary to have a time span.

Monostable multibibreaks 123 and 125 are AND
A signal is generated which controls gate 104 to selectively inhibit gate pulses equal to the number of clock pulses present at the output of AND gate 105 along with gate 105 from being provided to divider 106 .

In other words, the gate 104 responds to the output of the monostable multi-bi break 125, as shown in waveform (■) in FIG.
It operates to ``gate out'' a number of clock pulses equal to the number of pulses passing through AND gate 105 provided to divider 106 .

According to the invention, this action performs automatic time interval ranging by "shifting" the output signal of divider 106 by a time interval directly related to the number of clock pulses present at the output of AND gate 105. .

This in turn causes the output of flip-flop 110 to switch from a low state to a high state and back to a low state within one clock pulse time interval, thereby ensuring the desired accuracy of the time delay. measurements will now be performed.

Once auto range setting is done, flip-flop 1
The output signal Δt generated by 10 will be in steady state, amplified if necessary, side-waved and provided for reading or measurement by utilization means 124.

Since the time interval during which flip-flop 110 is in the second stable state represents a small fraction of the signal period, direct measurement is not desirable.

As discussed in the previously cited patent 3,271,666, it is useful to use a second flip-flop circuit operating at a 50% duty cycle to reduce the measurement error. be.

Flip-flop 111 is used for this purpose.

Therefore, flip-flop 111 is set to a high level state by the output of trigger 107 and reset by the 180° phase output of zero-crossing detector 120.

The signal developed at the output of flip-flop 111 also represents the residual delay time Δt, which is shown in waveform K of FIG.

The output signal from flip-flop 111 is supplied to meter 128 or analog-to-digital converter 129 via low-pass filter 126 and amplifier 127.

The residual delay time interval Δt is measured by the visual display on meter 128.

The output of the analog-to-digital converter 129 is used by the utilization means 12
4, which is then stored in the counter 131.

The signal Δt representing the remaining time interval stored in the counter 131 and, of course, the time interval NT stored in the counter 130 are applied to an adder circuit 132.

A signal representing the total time interval being measured is added to the summing network 1.
32 output, which is used as required.

For example, data representing measured time intervals may be stored for future use or transmitted to a remote station for analysis.

Figure 3 shows that when the received test signal is 'leading' the reference signal, i.e. when the zero phase reset trigger is leading the set trigger as shown in Figure 3 waveforms and C, respectively, the first 3 is a waveform representing a signal generated in the embodiment of the invention shown in the figure;

The operation of the present invention to perform automatic time ranging when the received test signal is ahead of the reference signal is essentially the same as described above for the delayed test signal, and will therefore be described in detail again. There's nothing to say.

For a leading test signal, the measured delay time is only longer.

Thus, as shown by waveform B in FIG. 3, the period of the signal produced by divider 106 is extended by a time interval that is greater than the "normal" period of the output signal produced by divider 106.

This causes the set trigger to be "shifted" by a time interval corresponding to the change in the output of divider 106, as shown in waveform C of FIG.

The shift in the position of the set pulse, as seen in waveforms J and K of FIG. 3, causes the reset pulse to "skip" in this example.

After this, flip-flops 111 (FIG. 1) are set and reset in the correct order to perform the desired measurement of the delay time interval Δt, as shown in the waveform of FIG.

Other similarities between the waveforms of FIGS. 2 and 3 can be easily seen by comparing their respective numbers.

To distinguish between lagging and leading test signals, counter 130 (FIG. 1) is preset to the desired module.

The maximum lag and advance time intervals are usually known from prior experience.

This example assumes that the maximum possible lag and advance time intervals are equal.

Therefore, counter 130 is preset to a count of 4 to produce an output as follows.

Therefore, when measuring a delayed test signal as described above, counter 130 (FIG. 1) is incremented by two by the two clock pulses (waveform F in FIG. 2) provided by AND gate 105. , proceeds from the initial counting state 4 to counting state 6.

This count indicates that the test signal lags the reference signal by a time interval of 2T plus Δt.

where T is the time interval between adjacent clock pulses and Δt is the residual time interval stored in counter 130.

Similarly, when measuring a leading test signal, counter 130 is connected to AND gate 105, also as described above.
(waveform F in Figure 3)
) by 6 clock pulses, and the initial count is 4.
Proceeds from the state to the count 3 state.

This indicates that the test signal leads the reference signal by a time interval of IT plus Δt.

Therefore, an indication of whether the test signal lags or leads the reference signal is easily performed.

FIG. 5 is a simplified block diagram of a time interval measurement scheme including uncertainty removal means according to the invention.

In this case, the reference pulse generator 101 generates a stable pulse signal having a predetermined time interval as described above.

The output of pulse generator 101 is connected to controllable gate 204
and delay 205 and one input of AND gate 206.

Gate 204 is any of a variety of controllable switching elements known to those skilled in the art.

AND gate 204 is advantageously a NAND gate, which normally operates to feed the pulse signal output of generator 101 to divider 207 and to one input of NAND gate 208.

The delay 205 is an AN whose inputs are connected in common.
A D gate may also be used.

Divider 207 operates to generate a pulse signal with a period equal to an integer multiple of the time interval between pulses provided by generator 101.

In this embodiment, although this does not limit the scope of the invention, divider 207 performs a 6:1 division in response to clock pulses as shown in waveform A of FIG. A signal as shown by the dotted line of waveform B in FIG. 6 is normally generated.

The solid line signal shown in waveform B in FIG.
shows the output of

Shifting the output from divider 207 relative to the clock pulses, as shown in waveforms A and B of FIG. 6, respectively, is accomplished by delays inherent in divider 207.

This delay time interval is corrected by using a monostable multi-by-break 209.

Monostable multi-bi break 209 responds to a negative change in the output signal from divider 207 by generating a pulse signal as shown by waveform C in FIG.

The output of monostable multivibrator 209 is applied to set inputs of zero phase flip-flop 210 and 180° phase flip-flop 211, and is also applied to gate monostable multivibrator break 212.

The unstable time interval of the monostable multi-bi break 209, that is, the pulse width of the signal shown in waveform C in FIG. , flip-flops 210 and 211 are in a high level state,
and adjusted to be switched to a low level state.

This configuration improves measurement accuracy and is important for minimizing uncertainty in autoranging.

That is, the positive transition of flip-flop 210 occurs in accordance with the clock pulses, further ensuring that the circuit does not range continuously.

The received signal to be measured is input to input terminal 115.
to the zero-crossing detector 220 via.

Detector 220 generates a pulse signal representative of the reference position of the test signal in response to the applied test signal.

It is desirable that the positive zero crossing position of the test signal be detected as shown in the waveform of FIG.

Detector 220 also generates a pulse signal representing the location of the negative going zero crossing of the test signal, as shown in waveform N of FIG.

That is, detector 220 generates signals representative of the zero phase position and the 180° phase position of the received test signal.

Although a 180° phase position of the test signal was used in this example, any other fixed phase position may equally be used in practicing the present invention.

The pulse signal representing the zero phase position of the test signal as shown in the waveform of FIG.
given to shift.

Monostable multi-bi break 221 normally has a high state output and generates a pulse signal as shown in waveform E of FIG. 6 in response to a positive change in the zero phase output of detector 220.

The instability time of the monostable multi-bibreak 221 can vary, which is used in accordance with the present invention to eliminate uncertainty in automatic time ranging.

Details related to uncertainty removal are discussed below.

The output of the monostable multi-bi break 221 as shown in waveform E in FIG. 6 is applied to the reset input of the zero phase flip-flop 210.

This causes flip-flop 210 to switch from a high state to a low state.

According to the invention, the width of the signal developed at the output of flip-flop 210 is within the time interval between adjacent clock pulses generated by pulse generator 101.

As mentioned above, the act of the present invention that accomplishes this purpose is referred to as "autoranging."

The output of flip-flop 210, as shown in waveform F of FIG. 6, is provided to a second input of AND gate 206 and to uncertainty detector 230.

Details of the operation of uncertainty detector 230 are discussed below.

Operation of AND gate 206 is simple.

Gate 206 allows clock pulses to pass only when the output of flip-flop 210 is in a high state.

A clock pulse that is allowed to pass, as shown in waveform G of FIG. 6, is provided to one input of AND gate 222.

The signal generated by the gate monostable multi-by-break 212 as shown by waveform H in FIG.
A second input of gate 222 is provided.

As is well known to those skilled in the art, NAND gate 222 generates a low state signal when high state signals are applied to both inputs simultaneously.

Thus, in accordance with features of the present invention, the signal generated by monostable multi-bi break 212 has the waveform C of FIG.
The pulse width is adjusted so that the NAND gate 222 operates so as to generate only one negative transition, as shown in the waveform 2 in FIG. 6, during each cycle of the reference signal as shown in FIG. have.

The signal generated by NAND gate 222 is then provided to trigger gate monostable multi-by-break 223.

The output of gate monostable multi-by break 223 is NAN
A second input of D-gate 204 is provided.

Gate monostable multi-by-break 223 responds to the output from NAND gate 222 to generate a low level signal as shown by waveform J in FIG.

The gated monostable multi-by-break 223 is arranged so that only one clock pulse is generated during the unstable time interval.

Therefore, AND gate 206, gate monostable multi-by-break 212 . It can be seen that NAND gate 222 and gated monostable multi-by-break 223 cooperate to generate a signal that controls NAND gate 204 to selectively inhibit clock pulses from being applied to divider 207.

As mentioned above, only one clock pulse is "gated out" or inhibited during each cycle of the reference pulse signal.

Therefore, the output of divider 207 is output from flip-flop 210.
During the first time interval when A is set and reset
It is shifted in equal increments until the total shift is equal to a time interval directly related to the number of clock pulses present at the output of ND gate 206.

In addition to performing automatic time ranging, this facilitates counting of gate-out pulses and is useful to minimize operational uncertainty.

In this example, only two clock pulses occur during the time interval in which zero phase flip-flop 210 is set and reset.

To effectuate the desired switching of flip-flop 210 during the time interval between adjacent clock pulses, as shown in waveform F of FIG. 6, only two clock pulses are required, as shown in waveform K of FIG. It is prohibited from being supplied to the divider 207.

Delay 205 and N
An AND gate 208 is used.

The NAND gate 208 has a delay 20 as shown in the waveform of FIG.
5 and the NAND gate 204 shown in waveform K of FIG.
In response to the output of , a number of clock pulses equal to the number of gated out pulses as shown in waveform M of FIG. 6 are provided to the utilization means 240 .

Because NAND gate 208 operates only when the clock pulse is gated out, counting errors that may be caused by noise signals are substantially eliminated.

Utilization means 240 accumulates the gated-out pulse count using, for example, a counter and uses it later to make the desired time interval measurements.

Once automatic range setting is performed, flip-flop 2
The output signal from 10 has a time width Δt, which represents the remaining time interval, which in steady state can be amplified if necessary and applied to a meter for reading or to a utility means. or

Direct measurement is not desirable because the time interval during which flip-flop 210 is in the second stable state accounts for only a small portion of the period of operation.

As discussed in the previously cited patent No. 3,271,666, it is advantageous to use a second 79771071 circuit operating at approximately a 50% duty cycle to reduce measurement errors.

Flip-flop 211 is used for this purpose.

Therefore, flip-flop 211 is set by the output of gated monostable multi-by-break 209 and reset by the 180° phase output of zero-crossing detector 220.

The signal generated at the zero output of flip-flop 211 appears as waveform O in FIG.

The output signal from the flip-flop 211 is sent to the differential amplifier 2.
25.

The 180° output of zero-crossing detector 220 is provided to a second input of amplifier 225 via adjustable resistor 226.

In practice, a smoothing filter (not shown) is used at each input of the amplifier.

Resistor 226 is used as a zero adjustment for configuring the system.

Amplifier 225 responds to the waveformed signal to generate a signal representative of the measured residual time interval Δt, as shown in waveform P of FIG.

The output of amplifier 225 is connected to meter 227 or analog
A digital converter 228 is provided.

The residual delay time being measured is visually displayed on meter 227.

The output of converter 228 is fed to utilization means 240, where it is combined with the time interval represented by the number of clock pulses previously fed via NAND gate 208 to obtain a measurement of the entire time interval. give.

This information is then used as needed.

For example, measured time interval data may be stored for future use or transmitted to a remote station for analysis.

An area of uncertainty exists when measuring time intervals that are close to zero or where the residual time interval is close to zero.

In such cases, the system may continue to attempt autoranging forever.

This tends to occur when the trailing edge of the signal generated by flip-flop 210 overlaps the flip-flop.

In such cases, the autoranging system may erroneously gate out a clock pulse, thereby delaying the setting of flip-flop 210 by the time interval of adjacent clock pulses. Therefore, the correct order of supplying the set and reset pulses to the flip-flop 210 is disrupted.

Therefore, the output of flip-flop 210 will have an abnormally long pulse width.

When performing autoranging, the system attempts to reduce the output pulse width of flip-flop 210 so that it falls within the time interval of adjacent clock pulses.

As a result of autoranging, a situation is again obtained in which the set and reset signals are out of order.

Therefore, the system cannot continuously autorange and take measurements.

Such conditions, ie, conditions in which continuous autoranging occurs, are detected and corrected in accordance with the present invention by sensing the output of flip-flop 210.

The condition of continuous autoranging is easily detected because the signal generated by flip-flop 210 has a significantly larger average value in the uncertain region than when correct autoranging has occurred.

Therefore, the output of the flip-flop 210 is the resistor 231,
A detection circuit including a resistor 232 and a transistor 236 is provided.

Transistor 236 is normally off.

The constants of resistor 231, resistor 232, and capacitor 233 are chosen to be sufficient to trigger NAND gate 234 only when the short-term average value of flip-flop 210 is greater than or equal to a predetermined value.

Therefore, as shown in waveform Q in FIG.
The voltage developed across 3 is provided to the input of NAND gate 234.

A high level state signal is provided to the other input of NAND signal 234. When the signal developed across capacitor 233 reaches a predetermined value, a negative transition occurs as shown by waveform R in FIG. , occurs at the output of NAND gate 234.

The output of gate 234 is provided to trigger an uncertain monostable multi-by-break 235.

One output of the uncertain monostable multi-bi break 235 is provided to a transistor 234, while the output of the other uncertain monostable multi-bi break 235 is provided to a flip-flop 237.

The unstable time interval of the uncertain monostable multi-by-break 235 causes the autoranging circuit to inhibit operation of the uncertain detector for a time interval greater than the maximum time interval required to cycle. It is set between a certain predetermined period.

Transistor 236 is used for this purpose.

Accordingly, in response to the positive output of the uncertain monostable multi-by-break 235, as shown in waveform S of FIG.
short circuit.

As shown in waveform T in FIG.
responds to the negative output of the uncertain monostable multi-bi break 235 to generate a change of state in its output, as shown by waveform U in FIG.

In this example, it is assumed that the output of flip-flop 237 was initially in a low level state.

However, if the output of flip-flop 237 was in a high state, it would be switched to a low state.

The output of flip-flop 237 is provided to transistor 238.

Transistor 238 is configured to either connect resistor 251 in parallel with resistor 250, connect resistor 251 in parallel with resistor 250, or disconnect resistor 251 from being connected in parallel with resistor 250. Operate.

Either of these states depends on the initial state of flip-flop 237.

In this example, flip-flop 237 is switched from a low state to a high state.

Therefore, transistor 238 is gated on and resistor 2
51 is connected in parallel to the resistor 250.

Resistors 250 and 251 are used to control the instability time interval of shifted monostable multi-bi break 221.

The constant values of resistors 250 and 251 shift The instability time interval of monostable multi-bi break 221 shifts depending on whether resistor 251 is connected in parallel with resistor 250 or disconnected.
The 21 unstable time intervals are chosen to decrease or increase by the above-mentioned time intervals.

A shift in the test signal causes a corresponding shift in the output of flip-flop 210.

Thus, the condition that originally created the uncertainty, namely the coincidence of the trailing edge of the output of flip-flop 210 and the clock pulse, is eliminated.

This normalizes the autoranging circuit and measures the desired delay time interval.

FIG. 8 illustrates the realization of shifting the unstable period of the monostable multi-bi break 221 by shifting the test pulse (dotted line in waveform E in FIG. 8) and the output of the flip-flop 110 (dotted line in waveform F in FIG. 8). ing.

The test signal supply to the reset input of flip-flop 210 is shifted, but the test signal supply to the reset input of flip-flop 211 (
The measurement of the remaining time intervals according to FIG. 5) remains unchanged.

Note that the signal provided to flip-flop 211 is not changed, but the uncertainty in autoranging is removed.

The present invention can be summarized as follows.

(1) In the time interval measurement method, means for generating a reference pulse at predetermined time intervals; means for generating a first pulse signal in response to the reference pulse; and means for generating a first pulse signal in response to a test signal; means for generating a second pulse signal representative of a first phase position; generating a control pulse signal selectively responsive to the first pulse signal and the second pulse signal; means for causing the first pulse signal to have a pulse width equal to the time interval between the occurrence of a predetermined change in state of the first pulse signal and the second pulse signal; and means for varying the pulse width of the control signal such that the pulse width of the control signal varies within a predetermined time interval.

(2) In the time interval measurement method, means for generating a reference pulse having a predetermined time interval; means for generating a first pulse signal in response to the reference pulse; and means for generating the first pulse signal in response to a test signal; means for generating a second pulse signal representative of a first phase position of the first pulse signal; generating a first control signal in response to the first pulse signal and the second pulse signal;
means for causing the control signal to have a pulse width representative of the time interval between the occurrence of a predetermined change in state of the first pulse signal and the occurrence of the second pulse signal; selectively prohibiting the reference pulse from being supplied to the first pulse signal generating means in response to the signal and the reference pulse, and changing the phase of the first pulse signal to the second pulse signal. and means for relatively varying the pulse width of the first control signal so that the pulse width of the first control signal is adjusted within a predetermined time interval.

(3) the means for inhibiting the first control signal and a second control signal having a time interval directly related to the number of reference pulses occurring between the pulse width of the first control signal in response to the reference pulse; means for generating a control signal; and switch means for inhibiting the number of reference pulses from being supplied to the first pulse signal generating means in response to the second control signal. This is the device described in item (2) above.

(4) the second control signal generating means includes a first gate means having first and second inputs and an output, the reference pulse being supplied to the first input; A signal is provided to the second input to energize the first gating means to pass a reference pulse during a pulse width time interval of the first control signal; timing means for generating the second control signal in response to a reference pulse generated in the first control signal, the second control signal having a predetermined phase relationship with the first control signal; 3. The device according to item (3), characterized in that the signal has a time interval surrounding the same number of reference pulses that occur during the time interval of the signal.

(5) the switch means includes second gating means having a first input, a second input and an output, the reference pulse being applied to the first input and the second control signal being applied to the first input; 2, the output is in circuit connection with the first pulse signal generating means, and the second gating means responds to the second control signal to generate the first pulse signal of the reference pulse. The apparatus according to item (4) is characterized in that supply to the pulse generating means is selectively inhibited.

(6) the timing means has a one-to-one relationship with the reference pulse generated at the output of the first gate means, and a first monostable multi-by-break that generates a signal having a predetermined time interval in response thereto; and a reference pulse generated at the output of the first gating means in selective response to a signal generated by the first unstable multi-by-break, each of which has an individual reference pulse. The device according to item (5), further comprising a second monostable multi-by-break that generates a signal having time intervals surrounding the pulse.

(7) the first control signal generating means includes bistable switch means including a first input, a second input and an output, the first pulse signal being applied to the first input; switching the bistable element from a first predetermined stable state to a second predetermined stable state, the second pulse signal being applied to the second input to switch the bistable element into the second predetermined stable state; The invention described in item (6) above is characterized in that the first stable state is switched from the state to the first stable state, and the first control signal is generated at the output.

(8) further comprising means responsive to the first pulse signal for generating a third pulse signal representative of an instant of a predetermined change in state of the first pulse signal; a first flip-flop circuit having an input, a reset input, and an output, the third pulse signal being applied to the set input, the second pulse signal being applied to the reset input, and the first The invention according to item (7) is characterized in that the flip-flop circuit generates the first control signal at the output in response to the second and third pulse signals.

(9) further comprising means for generating a fourth pulse signal representative of a second predetermined phase position of the test signal in response to the test signal; a second pulse signal including a set input, a reset input, and an output; a flip-flop circuit, the third pulse signal is applied to the set input, the fourth pulse signal is applied to the reset input, and the second flip-flop circuit generates at said output a signal representative of the time interval between the occurrence of said third and fourth pulse signals in response to a pulse signal of said first gate means and said second flip-flop circuit; and means for providing a measure of the time interval between a predetermined change in state of the reference pulse signal and the occurrence of a predetermined phase position of the test signal in response to a signal generated at the output of the test signal. This is the invention described in paragraph (8).

(10) means for generating a clock pulse at predetermined time intervals; dividing means for generating a first pulse signal in response to the clock pulse; and dividing means for generating a first predetermined pulse signal in response to the test signal; means for generating a second pulse signal representative of phase position; generating a predetermined change in state of the first pulse signal given the first pulse signal and the second pulse signal; first bistable switch means for generating a first control signal representative of the time interval between the occurrences of two pulse signals; first gating means applied to a first input, the first control signal being applied to the second input, the first gating means being responsive to the control signal to control the first control signal;
means for generating a clock pulse at the output during a time interval of a control signal; timing means for generating a second control signal in response to a clock pulse generated at the output of the first gating means; and second gate means for prohibiting the division means from receiving a number of clock pulses equal to the number of clock pulses generated at the output of the first gate means in response to the second control signal. This is a time interval measurement method that includes an automatic time interval range setting device.

(11) The timing means includes a first monostable multi-by-break that generates a first timing signal having a predetermined time interval in response to a clock pulse generated at the output of the first gate means; a second control signal selectively responsive to a timing signal of the clock pulse, the second control signal having a time interval that includes a selected one of the clock pulses; The method described in item 00) is characterized in that it includes a stable multi-bye break.

(12) means for generating a third pulse signal representing a second predetermined phase position of the test signal in response to the test signal; and means for supplying the first pulse signal and the third pulse signal. occurrence of a predetermined state change of the first pulse signal and the third pulse signal.
a clock pulse generated at the output of the first gate means and a signal generated by the second bistable switch means; 11y, further comprising means for providing a measure of the time interval between a predetermined change in the state of the first pulse signal and a predetermined phase position of the test signal in response to the test signal. This is the method.

(13) means for generating a reference pulse at predetermined time intervals; means for generating a first pulse signal in response to the reference signal; and means for generating a first reference position of the test signal in response to the test signal; means for generating a second pulse signal representing; generating a first control pulse signal in selective response to the first pulse signal and the second pulse signal; means for causing the first pulse signal to have a pulse width equal to the time interval between the occurrence of a predetermined change in state of the first pulse signal and the second pulse signal; 1
first means for selectively changing the pulse width of the pulse signal of the first control signal so that the pulse width of the first control signal changes within a predetermined time interval; selectively changing the pulse width of the second pulse signal, and supplying the first pulse signal and the second pulse signal to the first control signal generating means in a predetermined pulse time relationship; and second means for removing uncertainty in automatic time interval range setting.

(14) The second means selectively responds to the first control signal and generates the second control signal only when the average value of the first control signal exceeds a predetermined level. , means for changing the pulse width of the second pulse signal in response to the second control signal.

(15) The changing means includes controllable pulse generating means for selectively changing the pulse width of the second pulse signal in response to the second control signal.
) is the invention described in paragraph 2.

(16) The second control signal generating means includes means for detecting when the average value of the first control signal is thicker than the predetermined level. It is an invention of

(17) The detection means includes an integrating circuit and means for generating a third pulse signal only when the output of the integrating circuit exceeds a predetermined amplitude in response to the output of the integrating circuit, and The invention according to item (16) is characterized in that the control signal generating means further includes bistable switch means for generating the second control signal in response to the third pulse signal.

(18) the controllable pulse generating means includes a monostable multi-by break with a controllable unstable time interval, the controllable multi-by break being responsive to the second control signal and the second pulse signal; The invention according to the α-th force term is characterized in that a modification of the second pulse signal having a pulse width that changes is generated.

(19) The second control signal generating means further deenergizes the integrating circuit for a predetermined time interval in response to the third pulse signal, thereby causing the automatic time range setting circuit to (6) above, characterized in that one cycle of operation is completed before detecting the automatic time range setting condition.
This is the invention described in Section 1.

(20) The first pulse signal generating means includes dividing means, and the first means generates a number of reference pulses equal to the number of reference pulses generated during the initial time interval of the first control signal. and means for selectively sequentially inhibiting reference pulses from being provided to the dividing circuit until inhibited, thereby causing the pulse width of the first pulse signal to vary within a predetermined time interval. The invention according to item (13) above is characterized in that:

(21) the inhibiting means includes a controllable switch means; selectively deactivating the switch means in response to the first control signal, the reference pulse and the first pulse signal; The invention according to item (20) is characterized in that it includes means for generating a third control signal that sequentially prohibits the reference pulse from being supplied to the dividing means.

(22) responsive to a reference pulse signal and a test pulse signal representing a predetermined reference position of the test signal, providing a measure of the time interval between the occurrence of a predetermined change in state of the reference pulse signal and the test pulse signal; , in an automatic time ranging type time interval measurement system comprising a bistable switch element such that the pulse width of the reference signal is selectively varied to effect automatic time ranging, the pulse width of the reference signal generated by the bistable switch element The pulse width of the test pulse signal is selectively changed in response to the first control pulse signal generated, so that the reference pulse signal and the test pulse signal are applied to the bistable element in a predetermined pulse time relationship. A method of measuring time intervals is characterized in that it provides a method of measuring time intervals, thereby eliminating uncertainties in automatic time range setting.

(23) The changing means generates a second control signal only when the average value of the first control signal exceeds a predetermined level in response to the first control signal; (22), characterized in that it includes a controllable pulse generating means for changing the width of the test pulse signal in response to a control signal.
This is the invention described in Section 1.

(24) The second control signal generating means includes an integrating circuit that detects when the average value of the first control signal exceeds the predetermined level; and means for generating a control signal of the second control signal, the controllable pulse generating means including a monostable multi-by break with a controllable unstable time interval, and the controllable multi-by break generating a control signal of the second control signal. The invention according to item (23) is characterized in that a modified test pulse signal having a pulse width that changes in response to the test pulse signal is generated.

[Brief explanation of the drawing]

1 is a simplified block diagram of a delay time interval measurement circuit illustrating a first embodiment of the invention; FIG. 2 is a series of waveform diagrams useful in describing the circuit of FIG. 1; Figure 3 is the first
A series of other waveform diagrams useful in describing the circuits shown; FIG. 4 is a detailed view of the narrow pulse generator of FIG. 1; FIG. 5 relates to additional illustrated embodiments of the invention. FIG. 6 is a series of waveform diagrams useful in explaining the scheme shown in FIG. 5; FIG. 7 is a simplified block diagram of the apparatus shown in FIG. A series of waveform diagrams; FIG. 8 is yet another series of waveform diagrams useful for explaining the method of FIG. Explanation of symbols of main parts, 101...Signal generator, 106
...Dividing circuit, 120...Detection circuit, 110...First bistable switching element, 105,123゜124.104
...First control circuit, 230°221, Fig. 5...Second
control circuit, 104°204... controllable gate, 2
06,212°222.223...Prohibition circuit, 105...
...Gate circuit, 106...Pulse generation circuit, 123,1
25... Timing circuit, 104... Controllable gate, 111... Second bistable switch element, 124... Output circuit, 230... Uncertainty detection circuit, 221... Uft monostable multi-bi break, 232° 233.236…
...Integrator circuit, 234...NAND gate, 237...Third bistable switch circuit, 237.238,250,2
51... Control signal generation circuit, 235... Monostable multi-bi break.

Claims (1)

[Scope of Claims] 1. A signal generator for generating clock pulses having a predetermined pulse time interval, and a signal generator for generating a pulse reference signal having a period that is an integral multiple of the interval between pulses of the signal generator. a divider circuit responsive to clock pulses from the generator; a detection circuit responsive to the test signal to generate a test reference signal representative of a first phase portion of the test signal; responsive to a predetermined change in state of the pulsed reference signal from the splitter circuit for switching and responsive to a change in the state of the test reference signal from the detection circuit to switch to the other of the two states; a first bistable switch element that generates an output signal having a duration represented by the time interval between the pulsed reference signal and the test reference signal; In response to the output of and the clock pulse,
selectively inhibiting the number of clock pulses reaching the divider circuit to vary the pulse width of one of the pulses of the pulsed reference signal, thereby changing the width of the pulse time interval of the output of the first bistable switching element to a predetermined time period; An automatic scale range setting device in a time interval measuring method, characterized in that the device includes a first control circuit for changing within an interval. 2. In the automatic scale range setting device according to claim 1, the pulse width of the test signal is selectively changed in response to a predetermined output of the first bistable switching element, thereby changing the pulse width of the test signal. A time interval characterized in that it includes a second control circuit that eliminates uncertainty in automatic time interval range setting by causing the signal and the test signal to be applied to the bistable switch element in a predetermined pulse time relationship. Automatic scale range setting device in measurement method. 3. The automatic scale range setting device of claim 1, wherein the first control circuit selectively inhibits the clock pulses provided by the controllable gates so that each cycle of the pulsed reference signal An automatic scale range setting device in a time interval measurement method, characterized in that the device is configured to prohibit only a single pulse between intervals. 4. In the automatic scale range setting device according to claim 1, the first control circuit has a first input, a second input, and an output, and the first control circuit has a first input, a second input, and an output. a gate responsive to a clock pulse and an output of the first bistable switch element applied to a second input, upon receiving an output signal from the first bistable switch element, transmitting a clock pulse to a gate output; a timing circuit for generating a first control pulse in response to a clock pulse received from the output of the gate circuit; and a number of clock pulses generated at the output of the gate circuit in response to the first control pulse. An automatic scale range setting device in a time interval measurement system, characterized in that it includes a controllable gate for inhibiting equal clock pulses from being applied to the dividing circuit. 5. The automatic scale range setting device according to claim 1, comprising a detection circuit that also generates a second pulse signal representing a second predetermined phase position of the test signal, a set input, a reset input, and an output. a second bistable switch element having a second bistable switch element, a signal representative of a predetermined state change of the pulsed reference signal being applied to the set input, a second pulse signal being applied to the reset input, and a second bistable switch element having a second bistable switching element; a switch element responsive to the signal at its input to generate a signal representative of the time interval between the occurrence of the pulsed reference signal and the test signal;
Further, in response to the signals generated at the output of the gate circuit of the first control circuit and the output of the second bistable switching element, a predetermined state change of the pulse reference signal and generation of the test signal at a predetermined position are performed. An automatic scale range setting device in a time interval measuring method, further comprising an output circuit representing a time interval between. 6. In the automatic scale range setting device according to claim 2, the second control circuit selectively responds to the output of the first bistable switching element to adjust the average of the output of the first bistable switching element. Only when the value exceeds a predetermined level does the second
a shift monostable multi-bistable switch coupled to receive a second control signal for varying the pulse width of the test reference signal provided from the detection circuit to the first bistable switch element; An automatic scale range setting device in a time interval measurement method, characterized in that it includes a break. 7. In the automatic scale range setting device according to claim 6, the uncertainty detection circuit includes an integrating circuit and selectively responds to the output of the integrating circuit so that the output of the integrating circuit has a predetermined amplitude. NAND that produces a pulse output only when the
gate and the second gate in response to the pulse output of the NAND gate.
1. An automatic scale range setting device in a time interval measurement method, comprising: a third bistable switch circuit that generates a control signal; 8. In the automatic scale range setting device according to claim 7, the uncertainty detection circuit further responds to the pulse output of the NAND gate so that the automatic scale range setting device detects other uncertainty automatic range setting conditions. An automatic scale range setting device in a time-interval measuring system, characterized in that it includes a monostable multi-bi break which de-energizes the integrator circuit for a predetermined period of time in order to terminate the operation of the period.