GB1406639A - Range adjusting system for time measurement apparatus - Google Patents

Abstract

1406639 Time interval measurement WESTERN ELECTRIC CO Inc 7 Nov 1972 [10 Nov 1971 (2)] 51273/72 Heading H3H The time interval between a predetermined state of a pulse train and a test signal is determined by altering the phase of the pulse train until the interval is a minimum and then interpolating. The time interval may be a delay on a telephone line. Pulses from clock 102 are controlled in width at 103 and pass via gate 104 to divide by eight circuit 106 which has initially the dotted line output B. Positive going edges of pulse train B generate trigger pulses C (initially as shown dotted) which set bi-stable 110. The bi-stable output is fed to gate 105, to which clock pulses A are also fed. The test signal, which is delayed in phase relative to B is fed to input 115 of zero crossing detector 120 which has two antiphase outputs D (line 121) and J (line 122). Output D resets flip-flop 110 which initially has an output comprising the first pulse of train E and this pulse gates (as shown) two clock pulses (F) through AND gate 105. These pulses are fed to counter 130 and also to monostables 123 and 125. The outputs of monostable 125 (H) are of sufficient duration to prevent two clock pulses reaching divider 106 and the phase of output train B is therefore retarded to the position shown in solid lines. The output pulse from flip-flop 110 is now of duration #t-less than the period of clock pulses A. As this pulse represents a very small portion of the divider output period it is difficult to measure so the trigger pulses C are also fed to set flip-flop 111 which is reset by the antiphase zero crossing pulses J. The output of this flip-flop is a waveform (K) of fairly equal mark space ratio and this is low-pass filtered (126) amplified and the value of #t displayed on meter 128. This value is also converted to a digital signal by converter 129 and is fed to counter 131. The output of counters 130 and 131 representing coarse and fine parts of the time measurement are combined in summing circuit 132. Coincidence of set and reset pulses on flip-flop 110 may cause a large number of pulses to pass AND gate 105. Circuitry may be provided (Fig. 4, not shown) to integrate these pulses and, when the integral exceeds a predetermined value indicative of a coincidence, the time delay of a delay circuit in line 121 may be altered. The phase changing may also be carried out in a series of steps, each corresponding to the suppression of one pulse.