JPS58103041A - Microprogram controller - Google Patents

Abstract

PURPOSE:To simplify the constitution of hardware and facilitate the control, by controlling the clock, which determines the cycle of instruction execution, in address block units. CONSTITUTION:A microprogram memory 1 is divided into plural address blocks 1-1-1-4, and memories and microprograms different in speed are assigned to address blocks 1-1-1-4. In case of the processing of a micro instruction, the time required for the execution of this instruction is discriminated by the address of the instruction, and the clock generation cycle of a clock controlling circuit 4 is controlled by this discrimination signal, and a clock signal is transmitted to a pipeline register 7 and a control object 8.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a microprogram control device that performs control using a microprogram, and particularly relates to (1) improvement of a clock control means for controlling the progress of a microprogram.

y of a 1h control device that generally uses a microprogram.
No. 1 is roughly divided into two operations: (1) fetching of microinstructions and (2) execution of microinstructions. In operation (1), the microinstruction at the specified address is retrieved from the microprogram memory, and in operation (2),
The operation of the controlled object is controlled according to the microinstruction extracted in operation (1). At this time, for one instruction (1
), (2) in order and then the next instruction's operation (1) takes time, so generally the next instruction is fetched at the same time as the previous instruction is executed.

That is, a pipeline register is placed between the microprogram memory and the controlled object, and at the same time as the microinstruction in the pipeline register is executed, the next microinstruction to be executed is taken from the microprogram memory.
Set in pipeline register. The unit of this operation is one step, and a microinstruction is executed at the time of each step. The basic unit of operation of a microprogram control device is one step of this microinstruction, and all operations consist of a stack of operations of this step.

Therefore, increasing the operating speed of this step even a little is a major factor in improving the performance of the device.

The above steps of the microinstruction are controlled by a clock, and the period of this clock is determined by two factors: the time required to retrieve the microphone ui-N instruction and the time required to execute the microinstruction. Ru. The simplest method is to set the period according to the operation that requires the longest time so that all of these operations can be guaranteed.

However, although this method simplifies the hardware because the clock period is constant, it results in wasted time when executing fast instructions or when the transfer time from the micromemory to the pipeline register is different, which reduces the overall execution time. The speed will be slower.

To solve this problem, conventional methods have been used to control the step cycle depending on the type of instruction to be executed.
When issuing a microinstruction, a method is adopted in which the clock is advanced after waiting for a response from the micromemory. However, in the former method, it is necessary to specify the execution time for each microinstruction, and to do so, it is necessary to set a bit pattern for time specification in a part of the microinstruction, or to control the cycle by decoding the instruction. This has the disadvantage that the necessary hardware increases and time setting data must be created for each instruction. Unfortunately, in the latter case, there is a disadvantage that response control must be performed for each type of memory used, and additional hardware is required for both the clock control side and the memory control side. However, when a horizontal microprogram and a vertical microprogram are executed in the same device, the time required for each process is different, and response control with memory cannot handle this. Attempting to eliminate clock waste time in this way has conventionally had the disadvantage of complicating the hardware.

The purpose of the present invention is to solve these conventional drawbacks by adding simple hardware! I'm trying to solve it. Briefly explaining the present invention, the present invention (3) divides the microprogram memory into a plurality of address blocks, allocates memory and microprograms with different speeds to different address blocks, and when processing microinstructions, The clock is controlled by determining the time required to execute the instruction based on the address of the instruction. Examples will be described in detail below.

FIG. 1 is a block diagram of main parts of an apparatus according to an embodiment of the present invention.

In the figure, 1 is a microprogram memory, and the storage area is divided into four address blocks 1-1 to 1-4. For example, if the address is 0
When there are numbers 0 to 100, addresses 0 to 25 are allocated to address block 1-1, and other addresses are distributed to the remaining address blocks. In this embodiment, horizontal microprograms are stored in address blocks 1-1 and 1-2, and vertical microprograms are stored in address blocks 1-3 and 1-4. Note that DO is a data output terminal, and A is an address input terminal.

(4) A microprogram counter 2 specifies the address of the microprogram memory 1, and counts up every time a microinstruction is taken out from the microprogram memory 1, thereby controlling the progress of the microprogram.

3 determines which address block of the microprogram memory 1 is indicated by the address output from the microprogram counter 2, and the clock control circuit 4
Control signal (discrimination signal) 'fr: This is an address discriminating circuit that sends out a control signal (discrimination signal). All you need to do is determine which address block an address is in. The clock control circuit 4 controls the generation cycle of the clock according to the control signal from the address discrimination circuit 3, and sends the clock signal to the pipeline register 7 and the controlled object 8.

Further, 5-1 and 5-2 are micro program memories l.
This is a code converter that converts vertical micro-instructions output from the .

6 is a selector that selects one of the outputs from the valley micromemory block (some of which are given via the code converter), and the selection information for which one to select is based on control information from the address discrimination circuit 3. by. The pipeline register 7 is a register for setting microinstructions, and the microinstructions selected by the selector 6 are set therein, and the controlled object 8 is controlled by the output of this register.

In the above configuration, when executing a horizontal microprogram, the address block 1-1 of the microprogram memo January is counted by the microprogram counter 2.
, 1-2 is selected, and its output is directly transferred to the selector 6. The selector 6 switches to either address block 1-1 or 1-2, 10,0111, according to the output of the address discrimination circuit 3, and the microinstruction is transferred to the pipeline register 7 via this selector 6. Ru. Furthermore, when executing a vertical microprogram, the address blocks l-3, T-3 of the microprogram memory 1 are counted by the microprogram counter 2.
4 (7) is selected and its output is sent to the code converter 5.
It is converted into a horizontal type instruction by the -1 spanning code converter 5-2 and transferred to the selector 6. Then, the selector 6 selects 10,000 outputs from the code converters 5-1 and 5-2 and transfers them to the pipeline register 7.

As shown in this example, the transfer route for horizontal microinstructions is microprogram memory 1 → selector 6 → pipeline register 7, and the transfer route for vertical microinstructions is microprogram memory 1 → code converter 5 - 1, 5-2→selector 6→pipeline register 7, the time required for transfer is different between the two.

This difference in transfer time is determined by the address determination circuit 3 based on the output (address output) of the microprogram counter 2. That is, if the address indicates the address block 1-1, 12f, the address discrimination circuit 3 sends a control signal to the clock control circuit 4 to generate a clock with a period corresponding to the horizontal type instruction. If the address indicates address block (8) 1-3, 1-4i, it sends a control signal to the clock control circuit 4 to generate a clock with a period corresponding to the vertical type instruction. It is sent to the brine register 7 and the controlled object 8.

Therefore, since the microinstruction is transferred using a clock having an optimum cycle depending on the transfer time, no wasted time occurs.

FIG. 2 is a diagram showing an example of a time chart of the device shown in FIG. Vertical instructions V1 to V3 are executed using a clock with a period τh, which is the sum of t1 and the delay time t2 of the selector 6.
For example, as shown in FIG. 3(B), the retrieval and execution of
and the delay time t2 of the selector 6. Therefore, when executing horizontal instructions, the processing speed can be improved by the amount of time required for code conversion.

In the above embodiment, the selector 6 is provided between the microprogram memory 1 and the pipeline register 7, but the microprogram memory 1 and the code converter 5-1
．． , 5-2 can be wired-OR connected, the selector 6 can be omitted. Further, although the vertical type microprogram is extracted and converted into a horizontal type instruction before being set in the pipeline register 7, it may be changed to the horizontal type after being set in the pipeline register.

In this case, it is sufficient to control the clock according to the execution of the instruction.Furthermore, in this embodiment, an example will be given where horizontal and vertical microprograms are mixed. The invention can be applied to all cases where a microprogram can be divided into blocks and the programs in the blocks have different execution speeds.Of course, the invention is also effective even when the operating times of memories for microprograms are different. be.

As can be seen from the above explanation, according to the present invention, the microprogram memory is divided into ta number of address blocks,
When executing an instruction, the clock that determines the instruction execution cycle is controlled for each address block by determining which address block the instruction belongs to. Since the execution cycle is determined, the configuration of hardware such as an address discrimination circuit is simplified, and there is an advantage that the execution time can be easily specified since it is not necessary to specify it for each microinstruction.

[Brief explanation of drawings]

FIG. 1 is a block diagram of main parts showing an example of the device according to the present invention, FIG. 2 is a line diagram showing an example of a time chart of the device shown in FIG. 1, and FIG. 3 is a diagram of the clock used for horizontal and vertical instructions. It is a line diagram for explaining the contents. 1 is a micro program memory, 1-1 to l-4 are address blocks, 2-digit micro program counter, 3 is an address discrimination circuit, 4 is a clock control circuit, 5-1,
5-2 is a code converter, 6 is a selector (11) lid, 7 is a pipeline register, and 8 is an object to be controlled. Patent applicant: Fuji Electric Seizo Co., Ltd. (1 other person) Representative patent attorney: Hisashi Tamamushi (3 others) (12) +

Claims (1)

[Claims] A microprogram memory formed by dividing a storage area into a plurality of address blocks, a microprogram counter that controls the progress of micro 10 grams, and which block of the address blocks is indicated by the address output from the microprogram counter. an address discriminating circuit for discriminating whether or not there is an address discriminating circuit; a clock control circuit for controlling the cycle of a clock for advancing the step of a microinstruction according to a discriminating output from the address discriminating circuit; A microprogram control device comprising a pipeline register for setting microinstructions from a program memory.