JPS58102389A - Storage circuit - Google Patents

Abstract

PURPOSE:To reduce offset voltage distribution of a sense amplifier and to increase the density of a storage circuit, by connecting a compensating circuit to bit lines of the row circuit of a storage device, and compensating asymmetry between the sense amplifying circuit and bit lines. CONSTITUTION:In the row circuit of a memory which detects output signals from numbers of memory cells MC1-MCN through a sense amplifier SA, a correcting circuit CL1 is connected to the bit line BL1 of the row circuit to compensate asymmetry between the sense amplifier SA and bit lines BL1 and BL2. During this compensation period, information is outputted from none of memory cells and the sense amplifier SA is put in operation to store its operation result in the FF in the compensating circuit CL1, thereby detecting an output from a memory cell under control based upon the storage contents of the FF. Namely, specific charge is supplied to the input terminal of the sense samplifying circuit SA according to the storage contents. Consequently, offset voltage distribution of the sense amplifier is decreased to make a signal voltage from a memory cell lower.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a high-density storage circuit that stores information on a per-file basis.

Conventionally, this type of memory circuit has a large number of circuit groups (hereinafter referred to as row circuits) whose configuration is shown in FIG. 1, and a mechanism for selecting memory cells included in each row circuit.
It is provided with a mechanism for inputting and outputting data of a selected memory cell to and from the outside, and a mechanism for controlling the row circuit and the mechanism. As shown in Fig. 1, the row circuit consists of N memory precharge circuits PC, pc2', 1 sense amplifier circuit SA1, data input/output circuit DIO, and 2 memory precharge circuits (N is an even number of 1 or more). Bit line BL
,.

It is composed of BL2, two dummy cell circuits DC, , DC2, a precharge circuit PC1, a dummy cell circuit DC1, a memory cell MC, , MC2, . . .
MCN is connected to pit line BL1, precharge circuit PC2
, the dummy data output circuit DIO is connected to the pin I-i BL.
2, respectively, and the sense amplifier circuit SA is connected to the pins BL and BL, respectively.

Connected to both BL2. Memory cell MC,.

MC2,..., MCN are composed of a field effect transistor QM and a capacitor CM as shown in Fig. 2, and the drain of the field effect transistor QM is connected to the bit line B, and the source of the field effect transistor QM is connected to the bit line B. is connected to the first terminal of the capacitor CM, a DC voltage DD is supplied to the second terminal of the capacitor CM, and the field effect transistor QMO case is connected to the word line. Below, field effect transistor Q
The connection point (node) between the source of M and the first terminal of the capacitor CM is called NM. Dummy cell DC1* DC2 is the third
As shown in the figure, the field effect transistor Qlot l Q
It is composed of D2 and capacitor CD, and QDl
The drain of is connected to the bit line, the source of the field effect transistor QD+, and the source of the field effect transistor QD2
The drain of the field effect transistor Qo+ and the first terminal of the capacitor CD are connected to each other, the dart of the field effect transistor Qo+ is connected to the dummy word line DW, and the second terminal of the capacitor CD is supplied with the DC voltage vDD. and a field effect transistor Q. A DC voltage V,s is supplied to the source of transistor Q2. A tarock signal φ□ is supplied to the second key. Below, the connection point of the source of the field effect transistor QD+, the drain of the field effect transistor QD2, and the first terminal of the capacitor CD is N.
. It is called. As shown in FIG. 4, the sense amplifier circuit SA is composed of a field effect transistor Qs+ r Q82, and the drain of the field effect transistor QS+ and QS
The date of field effect transistor QS.2 is connected to the bit line BL, and the drain of field effect transistor QS2 and the date of field effect transistor QS. All of them are connected to the bit line BL,2, and a tarock signal φ is applied to the source of the field effect transistor Q81 and the source of the field effect transistor QS2. is supplied.

In explaining the operation of this conventional memory circuit below, the DC voltage vss is used as a reference voltage, and VDD
Assuming that is a high voltage, the field effect transformer (5) Nosta QM + Qol r QD2 + Qs+ +
It is assumed that Q82 is an N-channel type normally-off type field effect transistor. In this memory circuit, one bit of memory information is stored in each memory cell, and the memory information is associated with the level of the voltage of NM in the memory cell. In order to read stored information from a memory cell, one of the memory cells included in the row circuit is selected, the signal transmitted to the bit line by the selected memory cell is amplified by the sense amplifier SA, and the data is read out. The signal is output to the outside of the storage circuit through the input/output circuit DIO. As mentioned above, selection of a memory cell is performed by setting the word line connected to that memory cell to a high potential,
When the selected memory cell is connected to the bit lines SR, VC, the dummy cell circuit DC2 is selected (selection of the dummy cell is performed by setting the dummy word line connected to the dummy cell to a high potential). ), if the selected memory cell is connected to the bit line BL2, the dummy cell circuit DC1 is selected. In the following explanation, the value of the parasitic capacitance of the bit line (6) BL is designated as CB1, the value of the parasitic capacitance of the bit line BL2 is designated as CB2, the value of the capacitance of the condenser CM is designated as CCM, and the value of the parasitic capacitance of the bit line BL2 is designated as CCM, and the value of the parasitic capacitance of the bit line BL2 is designated as CCM. Let the value of capacitance be CCO.

A detailed explanation of the operation when memory cell MCN is selected will be given below. Before a read operation is performed, the bit lines BL,
, BL2 are set to high voltages V and D, and dummy cell circuit D
The connection point N of the dummy cell circuits DC, DC2 is set by setting the clock signal φ□ supplied to C1 and DC2 to a high potential and then to a low potential again. is set to the VS8 voltage, that is, the reference voltage. At this time, the clock signal φI) supplied to the sense amplifier SAK is set to a high voltage, and the field effect transistor qs+IQS2 is in a non-conducting state. Next, memory cell MCN and dummy cell circuit DC
When 1 is selected, the transistor QM of the memory cell MCN
and the field effect transistor Q13 of the dummy cell circuit DC.
．． Both become conductive. Since the connection point ND of the dummy cell circuit DC was set to the reference voltage (OV), when the field effect transistor QD+ becomes conductive, the charge on the bit line BL is transferred to the capacitor C of the dummy cell circuit DC.
If the connection point NM of the parasitic capacitance MCN between the bit line BL and the bit line BL is at the voltage vDD, the voltage of the bit line BL2 remains at VDD even if the memory cell MCN is selected. Conversely, if the connection point NM of memory cell McN is 0 [V], memory cell McN is selected and memory cell MCN
When the field effect transistor QM becomes conductive, the voltage on the bit line BL2 changes from VDp to "on".

The parasitic capacitances CB and CB2 of the power lines are set so that they are equal to each other.
2. Measured and vDD. In order to realize a high-density storage circuit with a potential intermediate between B2+63M-vDo, capacitor C
It is not possible to increase the capacitance value C6M of M, and the capacitance value C
6MIC0D is very small compared to the parasitic capacitance c811 CB2, so ear 7 cooling = VDD * 4th layer + 1 V
DDil-j: A voltage very close to vDD, and the voltage difference therebetween is usually several hundred millivolts or less. This minute bit line B
The sense amplifier S amplifies the potential difference between L1°BT and 2.
It is A.

As mentioned above, after a slight potential difference is applied to the bit lines BL, BL2 by the memory cell and the dummy cell, φ0 is set to a low potential, and the voltage of the bit line BL, BL2, which has a lower voltage, is applied. The charge is discharged through one of the field effect transistors Q81 or QS2 to lower the voltage on the bit line BL,.

The minute potential difference of BL2 expands and becomes a large amplitude signal.

When the memory cell MCN is selected and the connection point NM of the memory cell MCN stores a high voltage, the bit line BL1 is set to 0[ by the sense amplifier SA because the pit line is set.
V, ]K is set, and the bit line BL2 is kept at VDD. Memory cell MCN is selected and memory cell MC
The connection point NM of N is kept at (9) where a low voltage was stored, and the bit line BL2 is set to O [■].

In this way, the contents of the selected memory cell are taken out as a large amplitude signal on the pit line and output through the data input/output circuit DIO.

As explained above, the small signal transmitted from the memory cell to the bit line is amplified by the sense amplifier SA into a large amplitude signal, but the threshold voltage of the field effect transistors Q811 and QS2 that constitute the sense amplifier SA is same,
The gain constants of field effect transistors Q51+Qs2 are the same, and the parasitic capacitances CB1 . C
If B2 is the same, in principle, no matter how small the signal is, it will be correctly amplified. However, it is usually difficult to make the above circuit constants exactly the same, and there are some discrepancies. Therefore, the small signal transmitted to the bit line must have an amplitude within a certain limit, and for this purpose, the CcM must be larger than a certain limit, and this is the reason why this type of memory circuit has a high density. In order to eliminate the drawbacks of the conventional memory circuit described above, the present invention adds a sense amplifier circuit and a mechanism for correcting bit line asymmetry. Embodiments will be described in detail below.

As shown in FIG. 5, the row circuit of the memory circuit according to the first embodiment of the present invention is constructed by connecting a correction circuit CL1 to the bit line BL of the conventional memory circuit shown in FIG. The correction circuit CL is a field effect transistor Qcl + Q
c2 + Qc3 r Qc4+ Qcs l Qc6
, a capacitor C4, and resistors R, , R2, and is a field effect trannostar Q. 5 drain and Q. The drain of 4 is connected to the bit line hole, and the field effect transistor Q is connected to the bit line hole. 3 sauce and Q. The drain of field effect transistor Q is connected to rL. 2 sauce and Q. The drain of No. 1 is connected to the first terminal of the capacitor C1, the source of the field effect transistor QC1 is supplied with a DC voltage VSS, and the source of the field effect transistor QC4 is connected to the first terminal of the capacitor C1. 2-1-Kate Q. 5 drain and Q. 60 pieces 5-1- are connected to the first terminal of resistor R4, and the drain of field effect transistor (11) and the drain of QC5 are connected to the first terminal of resistor R2.
The field effect transistor Qc is connected to the terminal of
DC voltage VSs is applied to the sources of s and QC6, and DC voltage VDD is applied to the resistors R1 and R2 and the second terminal of capacitor C1.
are supplied respectively, and the field effect transistor QC
In the case of 3, the zero check signal φ1 is applied to the field effect transistor Q. The clock signal φ□ is applied to the cell No. 1, and the field effect transistor Q is connected to the clock signal φ□. Clock signal φ is applied to 40K-1. The configuration is such that each of these is supplied. From then on,
Field effect transistor Q. 1 drain and field effect transistor Q. The connection point of source 2 is N. 1. Field effect transistor Q. 4 source and field effect transistor Qc
The connection point of the drain of No. 5 will be called NC2.

In the following explanation, as in the explanation of the operation of the conventional memory circuit described above, it is assumed that the DC voltage V8S is a reference voltage and is 0 [■], whereas the DC voltage VD1. is a high voltage, and electric field effect]・Lannostar is a high voltage unless otherwise stated.
Assume that it is an N-channel type and a normally-off type. Immediately after the power is turned on (12), the memory circuit of this embodiment is provided with a correction period during which all sense amplifier circuits are corrected. The operation of this embodiment during the supplementary 11th period is performed as follows.

First, the bit line BI-111'3L2 is set to a DC voltage V by Zoriciano circuits pc, pc2. Set to D,
Black.

signal φ1. is set from a high voltage to a low voltage to operate the sense amplifier SA. If there is a slight difference between the field effect transistors Qs+ and QS2 of the sense amplifier SA or between the bit line parasitic capacitors CB1 and CB2, only one of the bit lines will be at a high voltage depending on the difference. After the sense amplifier SA operates, the clock φ.

The voltage of the bit line BL1 is changed from a low voltage to a high voltage by resistors R, R2 and field effect transistor Q. 5゜QC
The signal is input to the flip-flop FF' formed by 6 and stored. In this manner, during the correction period, information regarding the asymmetry of the sense amplifier SA and the bit line is transmitted to the correction circuit C.
Freelough 0flow in L1, f Store in FF. If the asymmetry is the bit line BL.

If there is a tendency to make the voltage high, the correction circuit CL,
connection point N. 2 is set to a high potential, and in other cases (13), the connection point NC2 of the correction circuit CL1 is set to a low potential.

Next, the read operation of this embodiment will be explained. Prior to the read operation, the pit lines old □ and BL2 are set to DC voltage vno, and the connection point N of the correction circuit CL1. , and the dummy cell are set to 0 [V] by the tarock signal φ1 once becoming a high potential and then returning to a low potential.

Next, the word line W of the selected memory cell is set to a high voltage, and the dummy word line of the dummy cell connected to the bit line to which the memory cell is not connected is set to a high voltage, and between the bit line hole and BL2. A minute potential difference is applied to the storage information corresponding to the stored information to be read. After this, the correction circuit C
Clock signal φ1 supplied to L1 is set to a high voltage. If connection point N. If the voltage on the bit line BL is low, even if the signal φ becomes high, the voltage on the bit line BL will not change. However, connection point N. 2 is a high voltage, when the tarock signal φ1 becomes a high voltage, the bit line BL and the connection point N are connected. Since a current path is formed between the bit line BL and the capacitor C1, the charge on the bit line BL is redistributed between the bit line BL and the capacitor C1, lowering the voltage of the bit line BL. Bit line B pulled down by this redistribution
Let the voltage of L be vl. The voltage v1 is a voltage signal φ, which can be set by the capacitance value of the capacitor C1.
After the signal φ becomes a high voltage, the black signal φ becomes a low voltage and the sense amplifier SA starts operating.

Field effect transistors Q81 and Q8□ or bit line BL
, and BL2, if the same voltage is applied to the bit lines BL and BL2 to operate the sense amplifier SA, only one of the bit lines BL or BL2 will be discharged. In order for BL2 to discharge in the same way, it is necessary to apply an initial voltage difference to the bit lines BL and BL2. V from bit line BL1 to BL2. When the potential is set to high, the above bit line BL.

Assuming that a similar discharge occurs in and BL2, Vo is the so-called offset voltage of this sense amplifier circuit.

(When Vo is a negative value, it means that the above state occurs when BL2 has a higher potential than BLl by IVo+.) Offset voltage V. are field effect transistors QS1゜QS2
, depends on the parameters of bit lines BL, , BL2,
It is an amount that fluctuates due to chance during manufacturing, and its fluctuation range is set as Δ. In a first embodiment of the invention, the voltage V.

The gain constants of the bit line parasitic capacitances CB and CB2 or the field effect transistors QSI and QS2 are set so that the center value of is 100. Therefore the voltage ■. is probabilistically distributed between −−Δ and d. During the correction period, the sense amplifier SA operates under the initial condition that the bit lines BL and BL2 are at equal voltages. If is between -DΔ and 0, bit line BL remains at high voltage, bit line BL1 and line hole 2 are discharged, and the connection point N. 2 stores the high voltage, and if the voltage ■. is between O and D, the bit line BL1 is discharged to a low voltage and the connection point N
A low voltage is stored in C2. During a read operation, if connection point N. If a high voltage is stored on line BL1, the voltage on line BL1 is lowered by BL1 before the sense amplifier SA operates. If the capacitance value of capacitor C1 is designed so that v1 = 1, the voltage of sense amplifier SA will be ■. Ga-
Whenever it is between τΔ and O, the signal voltage of the bit line BL is lowered by 1, and the voltage V. The effect is the same as if the height was increased by 1, and the connection point N was sloppy. When a high voltage is stored in 2, the effective offset voltage (offset voltage considering the effect of lowering the voltage on the bit line BL by the correction circuit CL) voo is distributed from m- to yt. Connection point N. Offset voltage V when 2 and low voltage are stored. 8 is also distributed from m- to τ. In this way, according to this embodiment, the distribution of the offset voltage of the sense amplifier circuit caused by variations in various circuits and parameters during manufacturing can be significantly reduced. The required signal voltage can be lowered, the area of the memory cell can be reduced, and the density of the memory circuit can be increased.

As shown in FIG. 6, the configuration of the row circuit of the second embodiment of the present invention is constructed by adding a second correction circuit cr,2 to the row circuit of the first embodiment. The correction circuit CL2 is composed of a field effect transistor Q. 3 Dray (17) N and Q. The correction circuit CL1 is completely the same as the correction circuit CL1 except that the drain of the correction circuit CL1 is connected to the bit line BL2. In this embodiment, the offset voltage of the sense amplifier SA, Δ voltage, is V. Bit line capacitance etc. are set so that the center value of is -π. Therefore, the offset voltage 2 vo is stochastically distributed between 11Δ and τΔ.

The operation during the correction period is performed as follows. As in the case of the first embodiment, first, bit lines BL1 and BL2 are connected to voltage V
DD and clock signal φ. is set to a low voltage to operate the sense amplifier SA. If the first offset voltage V. If is between −DΔ and O, bit line BL, is set to a high voltage and bit aBI,2 is set to a low voltage. Offset voltage V. is between 0 and Δ, bit line B
L1 is set to a low voltage and bit line BL2 is set to a high voltage. After the sense amplifier SA operates, the correction circuit C
Tarock signal φ is supplied to L. is set to a high voltage, and the result of the operation of the sense amplifier SA is stored in the seventh lip-flop 0 in the correction circuit CL. In the first embodiment, Δ is set so that the capacitance value of C4 of the correction circuit CL is υ, - /IG+), but in the second embodiment, the capacitance value of C7 of CL is υ , − was previously set to be Δ. After writing the stored data to the correction circuit CL, set the bit lines BL and BL2 to the high voltage VDD again,
By temporarily raising the clock signal φ□ to a high voltage and returning it to a low voltage, the connection point Nc1 of the correction circuit CL is set to 0 [V].
Set to . Next, the correction circuit CL, the glue C2 signal φ1
set to high voltage. Offset voltage V. is between -lΔ and O, a high voltage is stored in the connection point Nc2, so the voltage of BLl is vDD-vl, that is, VDD-
is set to τΔ.

Offset voltage V. is between O and τΔ, the connection point N of the correction circuit CL. Since a low voltage is stored in bit line BL, the voltage of bit line BL remains at VDD and does not change.

Next, the clock signal φ. to a low voltage and the sense amplifier S
Operate A. Offset voltage■. is between O and τΔ, bit line BL is set to a low voltage and BL2 is set to a high voltage. If the offset voltage ■ is between 11Δ and 1τΔ, the voltage on the bit line BL1 is only lowered by 1Δ by the correction circuit CL, so the bit line BL1 is set to a high voltage.
BL2 is set to a low voltage. Offset voltage■. Ga-
If it is between Δ and O, the bit line BL.

Since the voltage of bit line BL is lowered by -Δ by correction circuit CL1, bit line BL is set to a low voltage, and BL2
is set to high voltage. The operation result of this sense amplifier SA is the tally clock signal φ of the correction circuit CL2. By raising the voltage to a high voltage, the resistors R4 and R2 of the correction circuit CL2 are
, are stored in a flip-flop composed of field effect transistors QC5 and QC6.

Thereafter, during the read operation, the correction circuit CL1. Control is performed to make φ of both CL2 high voltages. Correction circuit CL
2 connection point N. 2 is a high voltage, and when the reverse signal φ1 is a high voltage, the voltage to be lowered is v2. In the second embodiment, the correction circuit CL is adjusted so that τ2=τ.
2 capacitor C1 is set.

Offset voltage V. If it is once between -stop Δ and Δ, then 5. Due to the operation in the above correction period, the connection point N of the correction circuit CL1. 2 stores a high voltage, and the connection point NC2 of the correction circuit CL2 stores a low voltage, so it is lowered.
Effective) offset voltage ■. 8 is set between 1cho and 0. Offset voltage V. If is between −DΔ and 0, the correction circuit CL,
Since a high voltage is stored at the connection point NC2 between CL2 and CL2, the voltage is set between m- and - during a read operation.

- Voltage V. If is between O and τΔ5, a low voltage is stored at the connection point NC2 of the correction circuit CL due to the operation during the correction period described above, and the connection point N of the correction circuit CL2 is stored. Since a high voltage is stored in bit line BL2vo8, bit line BL2vo8 is set between - and K during a read operation. In this way, prior to the read operation, the connection point N between the correction circuits CL1 and CL2. After setting 1 to 0 [v] and selecting the memory cell, the correction circuits CL and CL
By setting the clock signal φ1 of bit line BL1.2 to a high voltage, the bit line BL1. The voltage of BL2 can be corrected so that the effective offset voltage is distributed between -■ and 100. The width of this distribution is different from τ in the conventional memory circuit, and the signal voltage that must be taken out from the memory cell to the bit line can be lowered, making it possible to increase the density of the memory circuit.

In the first embodiment, one correction circuit was provided, and in the second embodiment, two correction circuits were provided, but if three or more correction circuits are provided, the width of the effective offset voltage distribution can be further increased. It can be made narrower.

In the second embodiment, during the first operation of the sense amplifier SA within the correction period, the clock signal φ1 supplied to the correction circuits CL and CL2 is controlled to a low voltage, and the second sense amplifier SA operates. During operation, the clock signal φ1 supplied to the correction circuit CL is set to a high voltage, and the correction circuit CL2 is set to a high voltage.
The black signal φ supplied to the

It was necessary to control each to a low voltage. However, if a mechanism is added to set the memory contents of the flip-flops of the correction circuits CL and CL2 so that the cross point Nc2 is at a low voltage (22) prior to the correction period, the operation of the sense amplifier SA can be changed. In the first and second embodiments described above, in the read operation, after the memory cell and dummy cell are selected, the correction circuit CL
, and the clock signal φ1 of CL2 is set to a high voltage to perform a correction operation, but the bit line is connected to the precharge circuit pc4 . Voltage V at pc2. It may be selected at any time after the setting is set to D and until the sense amplifier SA is operated, and the order of selection of memory cells and dummy cells is not the same.

In the first and second embodiments described above, a flip-flop with a resistive load is used to store information regarding the offset voltage of the sense amplifier circuit obtained during the correction period. However, this is not an essential condition of the present invention;
In short, it is sufficient to have a means for storing information regarding the offset voltage, for example, the resistor J of the correction circuit CL shown in FIG.
+R2 is replaced with a P-channel field effect transistor, and the gate of the transistor replaced with resistor R1 is Q. The dart of the transistor connected to the gate of No. 5 and replaced with the resistor R2 is Q. A so-called complementary flip-flop configured in connection to the 6 darts may also be used. The resistors R1 and R2 of the correction circuit CL in FIG.
, except for the field effect transistor QC5+Q (26), a capacitor may be connected between the connection point NC2 and the DC voltage source, and the capacitor may be used as a means for storing information regarding the offset voltage. In this case, it is necessary to restore the information before it is lost due to leakage of the charge in the capacitor, and it is necessary to provide a correction period for writing the information not only immediately after power is turned on but also periodically.

In the embodiment described above, the field effect transistor Q is used to write information regarding the offset voltage of the sense amplifier circuit to the correction circuit. I was using 4.

However, as in the example shown in FIG. 17 is added to the correction circuit CL1 of FIG. 5, and its transistor Q is constructed. Drain of 17 bit #
Connect to BL2 and its transistor Q. The source of 17 is a field effect transistor Q. 6 and connected to the drain of field effect transistor Q. Clock signal φ is applied to 11 darts.

may also be supplied.

(25) The above embodiment has a configuration in which the offset voltage of the sense amplifier circuit is corrected by lowering the bit line voltage through charge redistribution between the capacitor c1 in the correction circuit and the bit line. However, it is known that the offset voltage of the sense amplifier circuit also changes depending on the parasitic capacitance of the bit line, and increasing the parasitic capacitance of one bit line is equivalent to increasing the initial voltage of that bit line. bring about an effect. A third embodiment of the present invention described below applies this principle to correct the offset voltage of the sense amplifier circuit.

As shown in FIG. 8, the row circuit of the third embodiment of the present invention replaces CL1 of the first embodiment of FIG. 5 with another correction circuit CL1.
The correction circuit CL1 is an N-channel normally-off field effect transistor Q. 8
r Qc9 + Qc12 r Qc15 "Channel type normally-off field effect transistor Q.7゜qc
lo' QCll and a capacitor c2, which is a field effect transistor Q. 7 source high QC
The source of 8 is connected to the bit line BL, and the field effect (
26) Lannostar Q. The drain of Qo7 is connected to the first terminal of capacitor C2, and the drain of Qo8 is connected to the drain of Qo70.

Source of QcH IQc+2 Drain+Qc, 0 Ke8
- The gates of the gate IQc13 are connected to each other, and the gates are at 0°11.

QC12 ke + l・+ Qc + o source IQl13
drain.

The drains of Qo9 are connected to each other, the sources of QC9 are connected to BL2, and the drain of the second terminal of capacitor C2, Qol, sQc+o has a DC voltage V. D is supplied, Q (source of HI3 and QC1
DC voltage VSS is supplied to the source of QC8 and QC8. A clock signal φ is applied to the 9th cell. The configuration is such that it is supplied with Field effect transistor Qc
The node to which the 7th gate is connected will be called NC3. In the third embodiment of the present invention, the field effect transistor Q is activated immediately after power is turned on. TO' QC+1゜Q
The flip flop consisting of C12+ QC[ is node N. 5 is set to a high voltage. Gain constants of jo l Qcl, +Qcl2, and QclS are set. As in the case of the first embodiment,
Immediately after the power is turned on, a correction period is provided. During the correction period (2
7) First, bit line BL1. The voltage of BL2 is set to the voltage vDD by the puliciano circuits PC1 and PC2, and the sense amplifier SA is operated. sense amplifier SA
, one of the bits pBL1, BL2 is set to a low voltage according to the offset voltage of the sense amplifier SA. End of operation of sense amplifier SA, clock signal φ. is set from low voltage to high voltage, and correction circuit C
The flip-flop in BL1. B
Set according to the voltage of L2 and clock signal φ again. is returned to a low voltage and the correction period ends. Thereafter, during the read operation, if node NC5 is at a high voltage, field effect transistor QC7 is always non-conducting, so the offset voltage of sense amplifier SA is not corrected, and conversely, node N
If C3 is a low voltage, field effect transistor Q. 7 is always conductive, the offset voltage of the sense amplifier SA is corrected in the negative direction. The sense amplifier SA is designed so that the center of its offset voltage and voltage distribution is a positive value, contrary to the case of the first embodiment, and the center of the distribution of the offset voltage and voltage is located at the node N.

3 is a low voltage, it is corrected to effectively (28) lower the offset voltage. In the case of this third embodiment as well, the effective offset of the sense amplifier SA)! The pressure distribution can be reduced by τ. By using a plurality of correction circuits CI,' as shown in FIG. 8, it is possible to further reduce the distribution of offset voltage and voltage. Further, in this embodiment, information input to the flip-flop is performed on bit lines BL1. Although it is possible to start from both sides of BL2, it is also possible to start from one side as in the first embodiment.

In a third embodiment, a field effect transistor Q is used to provide correction capacitance to the bit line. 7 and capacitor C
2 was used. However, a switched capacitor whose cross-sectional structure is shown in FIG. 9 may be used instead of the field effect transistor QC7 and the capacitor C2. The switched capacitor/P capacitor in Figure 9 is a P capacitor made on the surface of an N-type semiconductor substrate.
It consists of a shaped semiconductor region D, a thin insulating film E provided on the surface of the N-type semiconductor substrate adjacent to this region, and a metal electrode G provided on the thin insulating film E. The metal electrode G is at a node N on the line BL1. 3 Niso(
29) Both are connected. This switch! - The capacitor has a so-called MO8 structure, and when the voltage at the node Nc5 is low, an inversion region is formed on the surface of the semiconductor substrate immediately below the metal electrode G, and the inversion region is connected to the P-type semiconductor region. Since they are electrically connected, the capacitance between the P-type semiconductor region and the whole urine electrode G and the capacitance between the region and the semiconductor substrate increase. Therefore, the field effect transistor Q of the third embodiment.

This switched capacitor plays the role of 7 and capacitor C2.

FIG. 10 shows the configuration of a row circuit according to a fourth embodiment of the present invention. The row circuit of the fourth embodiment is different from the row circuit of the third embodiment.
Channel type field effect trannostar QC+4' QC1
51P channel field effect transformer Q. 16. It is constructed by adding a capacitor C5, and a field effect transistor Q. A field effect transistor Q between the source of 7 and the bit line 8510. 14 is inserted, and the clock signal φ2 is supplied to its gate, and a field effect transistor Q is inserted.

The source of transistor Q is connected to the bit line BL2. Clock signal φ2 is supplied to Q15, and the source of field effect transistor (30) Qc16 and Q. 15 drains are connected and Q
Case-1 of C+6 is connected to the source of Qc+o, and Q
The drain of C16 is connected to the first terminal of capacitor C3, and the second terminal of capacitor C5 receives DC voltage V.
The configuration is such that D+3 is supplied. In this example,
Off cell of sense amplifier SA (center of voltage distribution is O
As with the other embodiments mentioned above, a correction period is provided immediately after the power is turned on, and during the correction period, the pins BL, , BL2 are at equal voltage (VI
N)) and then the sense amplifier SA is activated. During this time, clock signal φ2 is set to a low voltage, and capacitors C2 and C3 remain disconnected from the B and 1 lines regardless of the state of the solid flop. Next, the black and red signals φ. is set to 1 voltage, and depending on the positive or negative offset voltage of the sense amplifier 8A, the free,
Set 70 Frotsuno. During a normal read operation, the clock signal φ2 is always at high voltage, and the bit line BL,
Alternatively, either capacitor C2 or C3 is always electrically connected to either BL2. sense amplifier 5A
(31) If the offset voltage Δ Δ is distributed in a width of Δ from 1 to 7, set the capacitance Δ value of capacitors C2 and C3 to the amount that effectively moves the offset voltage by 1. By doing this, the width of the offset voltage distribution after correction can be made uniform.

A clock signal φ2 is supplied to the correction circuit in which a plurality of correction circuits having the same configuration as the correction circuit CI shown in the fourth embodiment is used, and the information to be corrected has already been input to the internal flip 70 horn. It may be configured such that a high voltage is connected to the capacitor C or C of the correction circuit and the rabbit line, and a sense amplifier SA operation for obtaining correction information to be input to other correction circuits is performed. With this configuration, the width of the offset voltage distribution can be made even smaller than that of soil.

In order to correct the offset voltage of the sense amplifier circuit, another capacitor may be added in parallel to CD of the dummy cell circuit according to the correction data.

The present invention is applicable not only to (32) memory circuits using 1-tranonost type memory cells, but also to memory circuits using other memory cell formats.

In the embodiment described above, the storage mechanism of the correction circuit is configured such that the stored information is lost when the power is turned off, but if a programmable ROM is used, it is sufficient to perform correction immediately after manufacture.

Although the operation of one row circuit has been described above, one storage circuit often includes a plurality of row circuits, and the plurality of row circuits can be operated simultaneously.

As explained above, according to the present invention, the width of the offset voltage distribution of the sense amplifier circuit can be effectively reduced, and the signal voltage output from the memory cell to the bit line can be reduced. , memory cells can be made smaller.

However, according to the present invention, it is possible to increase the density of the memory circuit.

[Brief explanation of drawings]

FIG. 1 is a configuration diagram of a row circuit of a conventional memory circuit, FIG. 2 is a circuit diagram of a memory cell, and FIG. 3 is a circuit diagram of a dummy cell circuit.
FIG. 4 is a circuit diagram of the sense amplifier circuit, (33) FIG. 5 is a configuration diagram of the row circuit of the first embodiment of the present invention, and FIG.
7 is a block diagram of a row circuit according to a second embodiment of the present invention, FIG. 7 is a block diagram of a row circuit according to an embodiment of the present invention, and FIG. 8 is a block diagram of a row circuit according to a third embodiment of the present invention. Horizontal 1jν1 and FIG. 9 show C2 and Q in the third embodiment of the present invention. FIG. 10 is a sectional view of a switched carrier/P vine that can be replaced with 7, and is a configuration diagram of a row circuit according to a fourth embodiment of the present invention. MC,, MC2, · + MCN + Mcq+4.
,,, , MCN, memory cell, DC,, DC2/dummy cell circuit, SA/sense amplifier circuit', PC,, pc2/Briciano circuit, Dro data input/output circuit, BL, , B
L2 Bi, 1・Gen, φ. , φ0. φ. , φ1. φ2
・Clock signal, QM +QD1・CD2・QSl・Q
S2・QC+・QC2・QC3・QC4・QC5・QC
6'QC+7・Qc8' QC9+ QC+21 Q
C13'QC'14"C10 N-channel field effect transistor, QC7'QC101QC11' QC1
6”” channel type field effect trannostar, R1, R2・
...Resistance, CLl, CL2. CL/l, CLI'
,・Correction circuit (34) path, D...P type semiconductor region, G...metal electrode, FF
...Flip-flop, E-insulating film. Patent applicant: Nippon Telegraph and Telephone Public Corporation 1, (35)

Claims (1)

[Scope of Claims] (Li) In a storage circuit that includes a large number of memory cells for storing information input from the outside and a sense amplifier circuit for detecting electrical signals output from the memory cells, the correction period storage means for operating the sense amplifier circuit without outputting an electrical signal from the memory cell and storing the result of the operation; and storage means for detecting the electrical signal output from the memory cell. A storage circuit characterized in that the control means performs control according to the information stored in the storage means, and a correction circuit having the following: (2) The control means controls the input of the sense amplifier circuit based on the information stored in the storage means. The memory circuit according to claim 1, characterized in that it is configured to control electrical connection of a capacitor to a terminal.
(3) The control means is configured to control the supply of a constant charge to the input terminal of the sense amplifier circuit based on the information stored in the storage means. The memory circuit described in (1). (4) In a memory circuit having a large number of memory cells for storing information inputted from the outside and a sense amplifier circuit for detecting electrical signals outputted from the memory cells, electricity from the memory cells during the correction period is Storage means for operating the sense amplifier circuit without outputting a signal and storing the result of the operation; and control means for controlling detection of the electrical signal output from the memory cell using information stored in the storage means. A plurality of correction circuits having a plurality of correction circuits are provided for each sense amplifier circuit, and the storage of the plurality of correction circuits in the storage means during the correction period is sequentially controlled by information stored in other storage means. A memory circuit characterized by operating a sense amplifier circuit.