JPS58100151A - Data transfer device - Google Patents

Abstract

PURPOSE:To detect a transfer error by making a bit check on sent serial data. CONSTITUTION:A master station 20 converts data from a copying machine into seial data, which is sent to a subordinate station 30 through a terminal ANT. The subordinate station 30 converts the data into parallel data OUT2 for controlling an attachment such as a sorter. The serial data is sent from the subordinate station 30 to the master station 20 to control the copying machine by the parallel data OUT1 on the basis of data of the attachment. Aftr the data transmission, a bit check signal for the data is sent and a check is made on the reception side to detect an error in data transfer.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a data transfer device for mutually exchanging data between a copying machine main body and an additional device thereof, and particularly relates to processing of bit 2- in data transfer.

In general, copying machines that improve operability and precisely control copy quality include a data transfer device that exchanges various data between the copying machine itself and additional devices equipped with a sorter, input sensor, etc. is necessary. As shown in FIG. 1, this type of conventional data transfer device includes a central processing unit (CPU), a controller J,
Output driver A-/I, input interface/j, CP
Power supply circuit for U/4=- and additional scissors holder power supply circuit t7
Ik: Yes. The additional device 11 has a sequence controller, an input interface 7 and an eight 20A, an output driver A-J/MU, an output load-A, and an input sensor com, which are connected in response to various signals for mutual data transfer. For example, a flat cable consisting of several connecting wires is used.

The input interface /I of the copying machine main body // and the input interface scope υA of the additional device 110 can also be configured using a photo-cube as shown in 5 in FIG. 2 as a measure against wire tubes.

However, in any case, as the number of types of signals to be transferred increases, the number of connector pins also increases.

Not only are connectors and cables expensive;
*Results in deterioration of equipment reliability.
-Eversal Asynchronous Receiver It is called Transmission Transmission (UART) and has a transmission speed of 1OK to -0K.
There are data transfer devices that can perform serial transfers at speeds of (bits per second), but they are expensive, and although they have versatility, they are often unsuitable as data transfer devices between the copier itself and its attached devices. .

The aim of the invention is to obviate the above-mentioned drawbacks.

The main body of the copying machine and its additional device are each equipped with a microcomputer for serial data transfer, thereby providing a data transfer device that can be applied to existing copying machines as well as to containers.

Hereinafter, the present invention will be described in detail with reference to color planes.

FIG. 3 is a block diagram showing an example of the configuration of the main parts of the data transfer device according to the present invention. This data transfer device includes a compatible transmitting/receiving unit 20. JOIk.

Each is provided in the copying machine itself and additional equipment. The transmitter/receiver sections 〇 and 30 are each mounted on a single printed circuit board. / and an interface circuit. The transmission line connecting the transmitter/receiver units 0 and 30 is constituted by a connecting line connecting the antennas and a common ground. Therefore,
In implementation, a single wire connection AT can be used as a transmission line.

The micro-bini-tacho has the function of converting data from serial to serial and from parallel to serial.

nag-) K-connection [switch], master with J-co.
Configure the slave. In the illustrated case, the micro combinator L of the imager body transmitting/receiving section -0 is the master, and the micro combinator J/ of the additional device transmitting/receiving section 300 is the slave.

Microconvenience store taco text has power terminal voo
, ground terminal van and control terminals RT, CI.

When power is supplied to the power terminal VOO, a 9-set signal is supplied to the control terminal IT for initializing the system, and the control terminal XX is supplied to the control terminal XX.

An oscillation resonator is connected to X to oscillate a -MHz clock pulse, for example. By the way, i microcomputer/
, Jl, for example, ROM (read only)
It is possible to apply an i-microprocessor that accommodates 8AM (random access memory) and 8AM (random access memory) in an 1-chip.

In this data transfer device, when data is supplied from the main body of the copying room to the input terminal IN/ consisting of the terminals P//J-P/Jl of the transmitter/receiver section 0, the data is transferred to the amplifier section J.
, Jda amplifies the data, reads it into the microcomputer J/ via each terminal of the RJ boat, Rj port, and Transmit to JO. This transmitting/receiving section 3θ receives the serial data via the antenna terminal A) JT and inputs it to the R/boat of the 1-crocodile binatar J/. The microcomputer J/ converts the serial data back into parallel data and connects the 0 port and P
Each terminal of the port is supplied to an amplifier 32,39.

And amplifier JJ.

341 amplifies the parallel data and transfers it to an output terminal 0UT- consisting of terminals P2O1 to Pco1.

Similarly, when the slave-side transmitter/receiver 3σ transmits data to the master-side transmitter/receiver 20, the additional device inputs the data to the input terminal IN consisting of the terminals PJ/J-PJJ& to the amplifier Jj.

34, -v microcomputer 31. antenna terminal
! , microphone a convenience store taco 11 amplifier co j.

Through each J6 student, l1llll child P10/-P//
The output terminal OUT/K can be transferred. In this case, the micro combinator 31 performs parallel-to-serial conversion of data, and the micro-combinator 1 performs serial-to-parallel conversion of data.
can perform bidirectional data transfer.

FIG. 4 is a signal waveform diagram showing an example of a communication format applied to the data transfer device of FIG. 3.

The microcomputers 2t, 3/ execute steps ◎ to ◎ in step 5 as shown in the figure.
/ frame data transfer can be performed in row 5. In steps ■ and ■, the micro convenience store f on the master side
i2t and the slave side microcomputer J/ perform synchronized control of the transfer lock.Therefore, the microcombiator J/ controls the bit σ counter of the /7 frame from step 0 when the transmission twin is open. %m, m
By becoming 1o'', start step ■,
A transfer lock pulse with a period TM consisting of l bits is transmitted to the micro combinator J/ as TAJIK/.

During this period, the micro combiator J/ activates the timing aKJ from the rising edge of the θ bit and picks the period TM of the transfer lock pulse sent from the master side.
7 I times, calculate the average value T8 of the transfer lock period by performing arithmetic processing, and use the bits l to tj in step -■ to obtain the micro convenience store.

Return it to J/. Then, the microphone E2:I ambiator 1 checks whether the transfer lock cycle TM and the average value TB are strong or not. If it is '1' M) TIE, it is not possible to connect with the micro combinator 31, so the only way to do this is to set the transmission line to 10" in bit 16 of step 2 and notify the micro combinator Jl. , TM-T8"Q if available.

Micro; ambiator l bit lt in step ■
Set to 0″″ and start executing TASKg. The microcomputer J/ starts counting transfer locks from bit 1 in step (2).

, In the next step ■, ■, the microcomputer-l executes 'rA8Kj, first transfers the /Jl pit serial data consisting of bits /1 to J9 to the microcomputer J/, and then transfers the bits 30 to J of step ■.
A check bit consisting of 2 l pits is transmitted. Of these check pits, bit J0 may be an even parity bit, but in this embodiment, the previous bit
10'' to set the complement of 29, and bitcot
and bit 3° are clearly distinguished. The bit St in the check pit is set depending on the content of the data. In this embodiment, the bit St in the check pit is the same value as the pit code S, which is the seventh bit of the l-bit data.
Set. The check pit of JJ is set to 1σ" to represent the final bit, and this bit JJ#) $
Set @l''' at %d, and open the transmission line at bit JJ.

During the period when the micro combiator t is executing the TM 81J in steps s to s, the micro combiator J/ executes TASK 41 to read the transferred data.
converts the parallel data supplied to the terminals ptts to 1124I of the transmitter/receiver unit-0 into serial data and sends it to the transmission line via the antenna terminal ANT, and the microcomputer St receives the serial data, Convert it to parallel data again and send it to the terminal P of the transmitter/receiver 30.
Supply each to P Col. Therefore, the data supplied to the terminals P//ko to P/ko4IK at the input terminal IN/ of the transmitter/receiver 30 is sent to the corresponding terminal P-υ/-PJ/of the output terminal 0UT- of the transmitter/receiver 30, respectively. It will be distributed.

By the way, in step (3), the microcomputers J/ and J/ prepare to change the transmission/reception mode and change the data transmission direction. and.

In step ■, the microcomputer S on the slave side
t sets bit J to start transmitting data.
The micro combiator J/ starts counting transfer locks at the same time as it turns O''.

Since the transfer lock has already been synchronized in steps ■ and ■, the transfer lock cycle is reached in step ■! Tsubasa de/Jl pit serial data (Bit J!”-Tei 4)
can be sequentially transmitted to the micro-convenience store/tachometer.

Also, in Step @, 71 Cro Combiator J/
sends the 3-bit check pit (bits 37 to J9) to the microcomputer 1 in the same manner as in step (2). Thus, while the microcombiator 31 is executing the TAB direction for transmitting data, the microcomputer 2t.

The TAIIIC that receives that data is executed. Therefore, the transmitter/receiver part has a power terminal of 300Å! Terminal P at Nλ/
The data supplied to J~P Coco-tei is sent to the corresponding terminal P10/A-P of the output terminal 0'UT/ of the transmitting/receiving unit -〇.
// can be supplied to each. In step ◎, both microcomputers -/ and J/ open the transmission line and wait for the start of step ◎ of the frame in which the primary data transfer is performed.

No. SZ is a block diagram showing the configuration of main parts p in the microcombi five-tacho t, St. The micro-ambiator J/, 7/ has a control storage section st and a RAM, respectively.
(Random Access Method) Part I-1 Arithmetic Theory IJ&
It has a knit sJ and an akine mullet j#.

Here, the control memory section SlIF) ROM (read only memory) is.

It stores information necessary for controlling microinstructions, data transfers, lock cycles, etc. Decoder DCR is ROM
Decipher the data read from.

The program counter PC specifies the address of the ROM. Also, the stack 8'rK is 1, for example, Lxvo (
A set of registers used in a ``last in, first out'' format.

Next, lLa1i@zko consists of multiple memory areas,
Its address is specified by the X and Y address registers. Among the multiple memory areas, RAM/ stores data supplied to input terminal IN/ or input terminal IN-,
RAM is output terminal OUT / or output electronic 0U
Stores data to be supplied to T-.

Then, RAMj is connected to the antenna terminal MNT.

This is a memory area that stores serial input data transmitted from the monitor to the B/port. In addition, RAM @1/ has an interrupt counter that increments by +1 when there is a timer interrupt. There are a memory area for storing the transfer clock period TM1, a memory area for storing the fixed transfer lock period T8, a memory area for storing the management number of input/output data, etc.

Next, the 61st! The operation of this data transfer device will be explained with reference to the flowchart of the main program of El and the flowcharts of the subroutines shown in FIGS. 7 to 118.

In the microcomputer-/, J/, power is supplied and 1. When initialization is performed by a reset signal, the main program shown in FIG. 6 is started.

First, in step 1, Omu Kei is cleared, and in the 1st step, Mengko, subroutine 1! ODmu! This command "to DATA" is executed.
The microcomputers -/ and J/ respectively read the input information from the input terminals IN/ and IN- into the RAM/,
This is a routine for supplying output information read from the Ogo Mco to the output terminals OUT/, 0UT-. In step 1J, a transfer lock period TM is set in the RAM and a 1-interrupt counter is activated. Transfer lock cycle! As described above, M is written in the ROM, and the 0 interrupt counter, which determines the data serial transmission speed, increments its contents by +l every time a timer interrupt occurs.

In step &41, Micro Combiator J/
, J/ are respectively master or slave.

Then, since the microcomviator I is the master and the microcombiator J/ is the slave, the process moves to the first step, and in step 44I, subroutine 1/8 is entered, and step 44 is subroutine @TA8KJ.
” t/Execute. Therefore.

Microcomputer tacho/ is first bit 0 in period TM.
Transfer lock pulse is sent to transmission 2 input using l bits from bit 7 to 1 micro;
(See step (2) of Cll1i4H to keep the transfer lock period constant). Next.

Based on the measured transfer lock period T8, the micro combinator J/ sends back a transfer lock pulse across bit l and bit /j, and the micro combinator J/ receives the transfer lock (FIG. 4). (See step ■).

Microcomputer J/.

3/ performs synchronization control of the transfer lock cycle.

As a result, if the clock period is TMζT8, the mutual:1
We'll meet at Guiniecation. This determination is made in the subroutine "KIROR" in step 17, and the clock period TM! When it becomes qT11, @/ is written in the error 7 lag register.
" is input. Whether this error 7 blowfish is 11'" is determined by the microconvenience store tacho l in step at, and if the error flag is @, m, the process moves to step 49 and the error 7 data register is input. The process is reset and returns to step 61, but if the error flag is @0'', the next step 0fIC control is detected.

Here, if the error flag becomes @l'', as shown in step 0 of FIG.
Drop the transmission line to 10" and connect it to Micro Combiator J.
Inform l. However, if an abnormality occurs in the micro combinator 31 and the transfer lock cycle cannot be measured,
It is detected in the subroutine -ROR', the error 7 lag register becomes @l'', and the transmission line also becomes @on.

Now, in step 10, it is determined again whether the micro combinators J/ and J/ are masters or slaves, and the microphones o-:1 on the mass media side are
-f y @TAIKJ”, @TAIICI”
l x f rack l, executed in Kuco, and at the same time, the micro-viator J/ on the slave side executes the subroutine.
TAIKJ1”, “TE5IICJ”
, run with reference. In other words, the micro combinator
/but.

First, in step ① of Figure 4, the transmission line is
Next, perform steps ① and ② in the same figure.

1-bit serial data is transferred from bit/1 to J2, and a 3-bit check bit is transferred from bit 30 to J2. At this time, the microcombinators s,,,l
starts the data reception operation in step ■, and then starts the data reception operation in step ■
, ■ reads the 3-bit check pit that is serial data with /J bits. In this way, the microcomputer J/ executes the subroutine @TAIKJ", and the microcomputer J/ executes the subroutine "TAIK4".
(”t-execute.

Then, after the transmission port 1 is opened in step ■ in FIG.
0's subroutine "TAIKJ" 11 is executed, and at the same time, the microconvenience store Tacol executes the subroutine "TAIKJ" 11.
Execute $''.Microcomputer-/, J/
Step Kuko, 7*% each! Brutin l''
TM8kl'', ``TAIIKJ'' l When finished, the control returns to step 4JK for the primary data transfer.
be transferred.

The steps of the main program are as described above, but each of the steps will be explained in turn.

First, in the subroutine "10 DATA", Y
Icro Combiator Taco/, J/ has data management number Q~
Load the input data into RAM/ according to B
An operation of reading output data from AMJ is performed. Therefore, as shown in the flowchart of Fig. 1, when the satsushiten "10 DATA" is called, the data management number is cleared in step 21, and the data management number is input to the 凰mu M/ in steps fJ to z4. After the data is lost and the management number is cleared again in step S7,
Output data is read from BAMJ in steps Irg to DECO.

In other words, in StepCoco, 1, for example, the data management numbers @0'' to @/ assigned to the input terminals P//J to P/Koda of the copying machine body transmitting/receiving section J0 (Fig. 3), respectively.
/'', the input data is checked. Then, 1, for example, input electronic I with data management number "υ"! //
Step tJ depends on whether the data of J is 'l'' or “σ”.
Or step t*tC branches and data management number"
The input data is written to the RAM/ location corresponding to o''.

In the next step fj, the data management number is increased by 10 (one increment), and the data management number becomes 10.
” to @l”, so in step t4 the tube ** number becomes /
The check to see if it is "J" is 1NO", and control is returned to Step Kuko. The input data is taken into RAM/ according to the data management number, and when the data management number becomes -1", the check at step t6 becomes "YK8", so the control returns to step t.
will be transferred to Step it~Deco [jcf is the output data read out from RAMJ according to the data w increment number.
It is distributed to pH 2, but its control is in step 5.
This is because the actual contribution is the same as 1 to 16.

The explanation will be omitted.

In step 6J of the main program.

As described above, the RAM K transfer lock period TM is set and the 1 interrupt input 9 counter is enabled. When there is a timer interrupt, the interrupt routine of FIG.
0/~103 will be executed. That is, each time there is an interrupt, the contents of the interrupt input 9 counter are incremented by 1 and the interrupt counter overflows.
The Fukugu register will be set.

Microcombinator 2/ executes subroutine ``TAIIK/'' in step 4j of the main program. Figures 9 to 12 show the subroutines 1-1.
This is the 7a-chart of ``1/''. Subroutine ``T^
8/'', the micro combinatorial connects the transmission line via the antenna terminal NT to the transmission line.
After sending out a transfer lock pulse with a period TM consisting of repetitions of σ” and ’”/”, the micro combinator Jl
The period of the transfer lock pulse sent back from Tit-
l1l is determined. The transfer lock pulse of l bits consisting of bits 0 to ri is executed in steps 104I to 104O.
Antenna terminal ANT set and cable ``CNT''
This is done by alternating CLR'''.

Here, the subroutine "CNT CLR" executes step /J41. as shown in FIG. jJ! By clearing the 1st interrupt counter and checking the match between the contents of the 1st interrupt counter and the period TM (set in RAM K), the transfer is locked. ing.

In steps /J/ to I of the subroutine "TAB1C/", the slave side microcomputer st
The period of l-bit transfer lock pulse returned by Tit
To measure the master data, the microcomputer tacho/subroutine "MEAS[IRICt]" is used.

1 MU JItFIK/'' are executed alternately.

Figure 11111 is a flowchart of the subroutine 1-Den AZUREυ'', in which the contents of the work 2-flag register are checked in steps 7 and 7, and if it is 'llI, it is a return, but if it is '''υ', it is a step. /J? clears the interrupt carinter. Next, step /J?
g, it is checked whether the antenna electronic ANT is 'ml' or not, but the initial value of the antenna terminal ANT is ''l'.
Since the format has already been pre-written as shown in , the process goes to step /39 and a check is made to see if the contents of the interrupt counter are twice the transfer lock period TM. If it is less than or equal to XTM, control is returned to step lJl described above. Therefore, in the cycle 〒8- for the antenna electronic ANT to fall from @l'' to ``O''K, the control is step/31→step/Jf→step/11→step/, 7?...
... loops and goes over and over again, but...
At some point, the antenna terminal ANT v-0" is transmitted and 1
゜Antenna terminal ANT falls to ``Q''. At that time, proceed to step 1410-, store the contents of 1 interrupt input 9 terminal in the corresponding area of RAM with measurement clock cycle 〒8,
As a result, the period T8 during which the antenna electron ANT is @l'' can be determined II).

IL As mentioned above, step 5/31 → step/, 7? →
Even during the loop from step 1stt to step/J9, the interrupt routine is asynchronously repeating, and each time the interrupt routine is incremented by 9, the antenna frame remains unchanged. MuNT becomes ′θ′″:′
%, the 1-interrupt counter will eventually count the quant value XTM.

This indicates a failure in communication, so
In step II, an error hook is set in the program 2-7 lag register, and the control is returned to the program agram. However, since the measurement of bit 1 is limited and the operation is only to detect the fall of the antenna electron ANT from 1 to θ'', the 61I constant result is not adopted.

Sub#-f y "MEA8URI/" is the 12th
As shown in the figure, in steps 1' to 5, steps /412. /4!
It is a subroutine except that the branch condition of J is reversed.
Same as MEmu8υR1: 0''.

Thus, bit t~14! - When one foot of the return lock cycle 11I consisting of l bits is completed, the interrupt counter is cleared at step l-t of the subroutine "TAll/", and the error flag register is cleared again at the next step /30. A check is made.

As a result, if the content of the error 7 puffer register is ``l'', control is returned to the main program, but if the content is ``O'', control is transferred to step /J/. Step/, 7/ In VC.

61I5? The calculation of the average value of the clock period 〒8 is executed, but here, the approximate value is calculated by majority vote and the average value of the measured clock period T8 is calculated, and in step 13, the transfer lock stored in the K RAM is TM is rewritten. In the next step /JJ, the contents of one interrupt kacunta are compared with the transfer lock TM, and the interrupt kacunta continues counting until they match, and when the count is counted, control is returned to the main program.

In parallel with the above-mentioned subroutine @TASK/, the slave-side microcombiator J/ executes the subroutine '
Execute "TASK, 2". Is Figure 13 the flowchart? Here, what is the Stesive/Ni5-is that measures the period TM of the transfer lock pulse sent from the master expansion and processes the measurement results? It is almost the same as step /J/-tss of routine "TAIIK/", and step /s to send the clock pulse back to the master controller based on the measurement transfer lock period.
l-/? j is almost the same as steps 104I to 104I of the subroutine "T^8/". However, bit Q
As for the transfer lock period TMK, the 113 constant value itself is meaningless because it only detects a smooth fall at the antenna end.

Also, vk for which the III determination of the transfer lock τM of bit 6 has been completed, bit 7 is @l'', so step ljJ
Then, at the rising edge, the interrupt force 9 is cleared. Therefore, how to measure the transfer lock period TM? is performed for bits θ to 6, and steps /! during bit 70 period. J-/
jri is executed.

In addition, step /41! ~Sapruchiy in ljko
“MIAIIURlCO”, “MIa8URI
i'' consists of the steps of the flowchart shown in FIGS. 11 and 12 IJ, and includes steps lSl to
Subroutine y “CTRCLR” in 7J is #, 1
It consists of the steps of the 7cl-chart shown in Figure 0.

Figure 914 is a flowchart of the subroutine @IRROpi of step 17 in the main program. In this subroutine @ICRROR, the microcomputer tacho / and J/ are each 1τ and 8.

This is executed after “TASKJ” is finished, and bit t4<114 of the communication 7 automatic
A routine to determine the value of step ■) in Figure 4.

Referring to the flowchart in FIG. 14, Stella 7'
/71I clears the interrupt counter, and in step its, it is compared whether the contents of the interrupt counter and the transfer lock period TM match.If they match, the next In order to show that the transfer lock has been synchronized in step /74, the antenna register 5NT @
If they do not match, the error 7 lag register is set to 'ml'.
The power song and five power notes will be checked in step 7.

As a result, if the error flag is ``capi l'', step l
? After the antenna terminal ANT is set to 10'' at t, the control is returned to step/l!K. However.

If the error flag is @Om, step/? ? In step 1, the antenna terminal ^NT is set to l″l″.
At 10, a check is made again to see if the antenna terminal NT is l''.The increase is made by the Master Confucian or the Kisrep side, and the antenna terminal NT can be set to 10'' at any time to indicate an abnormality. This is because the antenna terminal ANT is @l'' in step 110.
If so, the control is moved to step Its #C, but if not, the error flag register is set to @/'' in step /1/ and the control is moved to step /l!r K.
Control is returned. Like this subroutine @E
In RROR'', subroutine ``TA8/'',
It is checked whether the error flag register is set at 'TAIKJ' or not, and if the error flag is set to 'ml', the antenna terminal ANT is set to @O'. If it is not set to ``@l'', an error exit of the opponent's sword is detected, and the antenna terminal MNT is set to 1 due to an error.
If it is set to 0", set the error flag register to @l".

Wait until bit 16 is completed, and the contents of interrupt-9 and the transfer 1st open period TM match, and antenna terminal 1 is connected at the time of rainbow.
The step of setting k"/"K and returning to the main program is executed.

Figures 1s and 16 are flowcharts of step 1 of the main program. The microcomputer on the master side executes this subroutine @TM8KJ''.

Transfer the micro combinator J/l/Cchi1 on the slave side. Referring to the flowchart in FIG. 916, in steps tgs and its, the antenna terminal NT is set to 10" and the subroutine @CTN CLR" is performed.
At the 0th step lt, where all bits of @O'' are sent, l-bit data consisting of bits /I'-19 is transferred, and FIG. Qυ! ”. Already in step 6 of the main program, RAM
Since the data to be transferred is stored in /, the subroutine "DATAOUT" reads out the data and serially transfers it according to the data management number.

As shown in No. 169, the data management number is cleared in step /94, and step it~/? At f, the data stored in the RAM/ location corresponding to the data management number of the power outage is read out.Then, the antenna terminal ANT is set to "0" or "11" depending on whether the -data is 10" or 11". Ru.

The control of the period of l bit set by 10% is performed by subroutine "CNT CLR" (10th
(see figure), the data management number is incremented by 1 in step CO01. Next, when the transfer of the data corresponding to the data management numbers @θ''' to @itl'' is completed, it is detected in step -0-, so the execution of the subroutine "DAT OUT" is completed, and the subroutine returns to “TAIlKj” Nosf
") F/l! JfC:t 71) CI-k is transferred. As mentioned in 5 above, the check bit consists of 3 bits from pit JO to J, and step:Pits~/
IK is used to determine the value of bit JO, which is the first bit of the check bits. In step its, it is checked whether the bit t is @l''', and if it is @l'', the antenna terminal 5NT is @O in step /14.
If it is set to 1', and if it is 0'', the antenna electron ANT is set to Ill i l'' in step 11. Here, the subroutine "CNT CLR" of step 11g
” is a subroutine that controls the transfer period of 1 bit, similar to step ltda.

Steps related to the a-th bit of the check bit/19~
Step 19 is almost the same as steps tts to tUt, but a routine is executed in which the value of pitco S is set as the value of bit 31. Antenna terminal A) in step /93
JT is set to 10''.

When the subroutine "CNT CLR" is executed in step /94I, the third bit of the check bit, PI), is sent to the first transmission line. Subroutine "TA"
In the final step /9! of 8Kj'', the antenna tla is set to @l''.

Figures 17 and 18 are flowcharts of the subroutine @TM8 to 4 ('' in step 1 of the main program. In this subroutine @TM8 to 41'', serial data transferred from the slave side is received. After doing 85 MJK stores, I checked to see if there were any transfer errors in the data.

If there is no transfer data, the step of transferring data to RAMJ [RAM, 2K] is executed.

Referring to the chart 70 in FIG. 17, first, in step-03, the interrupt output 9 counter is cleared, and in steps -04I and -O5, the contents of the interrupt output 9 counter are transferred, respectively, and the a-task cycle is reached. A check is made to see if it matches 1 times M and if the antenna terminal ANτ is set to ``1''. Even if it becomes one times the transfer lock period TM.

If the slave side does not start data transfer, that is, if the antenna terminal ANT does not fall to 'O'.

+ x The p-II's 11-crore computer computer I returns to the main control program immediately.If there is no data transfer from the slave side, there is no manual data transfer from RAMj to RAM-. No transfer takes place.

However, in step-〇S, the antenna terminal MNT
When it is detected that is @θ′″.

From that point on, the transfer cycle starts and the subroutine @CNT CLR'' is executed at step 06.

Then, once the period corresponding to bit 3 has passed.

The transferred data is captured, but in order to sample the data at the midpoint of the transfer lock period TM,
After the 1 min is adjusted in step -〇, the step JOt subroutine @DATA IN”
” is executed. This subroutine “DATA IN”
The data management number Vclt consists of the steps Koda to JJO that are stored in the RAM jK.

Therefore, in Step Cog, the data management number is cleared, and in Steps -5 to -17, the data transferred to the antenna frame NT is stored in the RAMJ location determined by the data management number of the PFt foot. Stored・In the next step, subroutine @
By executing ``CNTCLR'', the transfer lock period TMK@e is controlled, and furthermore, in step J-?, the data management number is incremented (+l), and in step J0 A check is made to see if the data management number has become ``''/J'', and if it is less than -l-'', step 2! tK control is returned and when it becomes JR, it is moved to the subroutine @TAillCda.

, in this subroutine ``mTM8.''

Sampling is performed at the midpoint of each bit (see Figure 4), and this bit 7 is the first bit of the 3 check bits, and its value is set in a complementary relationship with the value of bit 7. . Therefore.

In steps 〇9 to ko13, the check is performed. First, if the bit toughness is 1θ" in step 〇t,
In step 210, it is checked whether bit 414 is 11" or not. As a result, if bit 6 is 10", there is no complement relationship with the bit tough value, so in step 1-, check miss flag register is set to 1
Next, the control is the Stepco/J subroutine.”
CNT CLR''. However, bit reference 1 is
l'', the control remains the same as Stepco/J
It will be moved to. Also, if bit number 7 is 1 and bit number is IIl, step code j2/
/ is detected and the flag register is set, but if bit tough is @l'' and bit reference 6 is ``Q'''', the controller is directly transferred from step code 09.:11/' to step code. Moved to IJK.

In the next step, from lj to ljk, a check is made to see if the bit at, which is the cobit of the check bit, and the bit dako have the same value. In addition, Stepco/
At 1, it is checked whether bit 449, which is the first bit of the check bit, is 1 or 5. If it is 'l', the check miss flag register is set at step here O, but if it is @0' and it is tearing, the control is Stepco 1
Moved to 1. Finally, in step 1, it is checked whether the check miss flag register is 11 or not, and it is checked whether there is any error in data transfer. And if the check miss flag register is not @l”,
The data in RAMJ is written to Ou^M-, but 'O''
If so, after the check miss flag register is reset, control is returned to the main program, and data in IAMJ is not written to RAM-.

By the way, please refer to Figures 1s to 18.

Mainly the master side sub blue differential BKJ"#
``TAIK4I'' vAs explained, the slave side subroutine @TAB section furnace'' (step J of the main program).

1Tm8KJ'' (main program step)K
However, since it is almost the same, that explanation will be omitted.

As mentioned above, according to the present invention, a micro-ambiator is provided in the copying machine main body and its attached device to perform data conversion and parallel-to-serial conversion, and to handle bit errors during transfer. Yes, data can be transferred serially to each other.

However, the number of connector bins that connect four microcomputers is extremely small, and error handling can be performed easily and reliably especially when a bit error occurs during data transfer, resulting in highly reliable data transfer. equipment can be provided.

Moreover, since the present invention has a simple configuration, it can be easily applied to existing copying machines.

[Brief explanation of the drawing]

1 and 2 are block diagrams showing a conventional data transfer device, and FIG. 3 is a block diagram showing an example of the configuration of the main part of the data transfer device according to the present invention. Fig. 4 is a signal waveform diagram showing the communication format, Fig. 5 is a block diagram of main parts of the microcomputer applied to the present invention, Saa is a flowchart of the main program, and Figs. 7 to 18 are subroutines. This is a flowchart. , 20... Transmission/reception unit for the copying machine main body. This is the master side microcomputer. -1, Jco...Master/slave changeover switch. KO3-J4, 33-34...Amplifier. 30... Transmission/reception unit for additional device. St... Slave side microcomputer. 51... Control storage unit, S code...8 Ms. jJ... Arithmetic logic unit, sv... Accumulator. RAM...Random access memory 2DCI...
Decoder, ROM...Read-only memory. PC...Prime counter, ITK...Stack. Patent applicant Canon Co., Ltd. Figure 12

Claims (1)

[Claims] The copying machine main body and its additional device I are each provided with a data transfer micro combiator having a program for serial-to-parallel conversion and parallel-to-serial conversion of data. Data characterized in that when serial transfer is performed in row 5, an error in the serial transfer is detected by a pit check of the data, and if the error is detected, the serial data of the previous frame is output as parallel data. Transfer device.