JPS5799815A - Automatic equalizer - Google Patents
Automatic equalizerInfo
- Publication number
- JPS5799815A JPS5799815A JP17688580A JP17688580A JPS5799815A JP S5799815 A JPS5799815 A JP S5799815A JP 17688580 A JP17688580 A JP 17688580A JP 17688580 A JP17688580 A JP 17688580A JP S5799815 A JPS5799815 A JP S5799815A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- value
- logical
- automatic equalizer
- output
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
- H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
- H04L25/03006—Arrangements for removing intersymbol interference
- H04L25/03012—Arrangements for removing intersymbol interference operating in the time domain
- H04L25/03019—Arrangements for removing intersymbol interference operating in the time domain adaptive, i.e. capable of adjustment during data reception
- H04L25/03038—Arrangements for removing intersymbol interference operating in the time domain adaptive, i.e. capable of adjustment during data reception with a non-recursive structure
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Filters That Use Time-Delay Elements (AREA)
- Cable Transmission Systems, Equalization Of Radio And Reduction Of Echo (AREA)
Abstract
PURPOSE:To prevent overcorrection of an automatic equalizer or divergence of the system even if an impulse noise occurs in the transmission line, by inhibiting the correction of the automatic equalizer for a constant time when the average value of the amplitude of receiving data exceeds a constant value. CONSTITUTION:Receiving data RD is given to an averaging circuit 7; and if receiving data having an abnormally large amplitude is given to the circuit 7, a large value appears in the output. The output of the circuit 7 is inputted to a discriminating circuit 8 and is compared with a predetermined constant value. When the average value exceeds the constant value as the result of the comparison, the circuit 8 outputs logical 1 to a timer circuit 9. When receiving the output of logical 1 of the circuit 8, the circuit 9 transmits logical 0 for a constant time. A gate circuit 10 is closed for the time of logical 0 to prevent the excessive error quantity from a discriminator 6 from being inputted to an adder 7. Thus, correction of the automatic equalizer is inhibited to hold the correction quantity, which is stored in a register 2, in the value just before abnormality.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP17688580A JPS5799815A (en) | 1980-12-15 | 1980-12-15 | Automatic equalizer |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP17688580A JPS5799815A (en) | 1980-12-15 | 1980-12-15 | Automatic equalizer |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5799815A true JPS5799815A (en) | 1982-06-21 |
Family
ID=16021459
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP17688580A Pending JPS5799815A (en) | 1980-12-15 | 1980-12-15 | Automatic equalizer |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5799815A (en) |
-
1980
- 1980-12-15 JP JP17688580A patent/JPS5799815A/en active Pending
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