JPS5797710A - Power amplifying device - Google Patents

Power amplifying device

Info

Publication number
JPS5797710A
JPS5797710A JP55174264A JP17426480A JPS5797710A JP S5797710 A JPS5797710 A JP S5797710A JP 55174264 A JP55174264 A JP 55174264A JP 17426480 A JP17426480 A JP 17426480A JP S5797710 A JPS5797710 A JP S5797710A
Authority
JP
Japan
Prior art keywords
output
pwm
signal
auxiliary signal
dsb
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP55174264A
Other languages
Japanese (ja)
Inventor
Atsushi Ogawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP55174264A priority Critical patent/JPS5797710A/en
Publication of JPS5797710A publication Critical patent/JPS5797710A/en
Pending legal-status Critical Current

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  • Amplifiers (AREA)

Abstract

PURPOSE: To prevent the occurrence of a DC offset for no signal even if the pulse width of PWM.DSB waves is limited, by including an auxiliary signal, which becomes a DC offset cancelling pulse, in PWM.DSB waves for no signal.
CONSTITUTION: The output from a PWM full-wave rectifying part 11 and the rectangular wave signal from a clock oscillating part 12 are operated for AND, and the output is applied to a PWM.DSB control signal generating part 13. The auxiliary signal from an auxiliary signal generating part 15 is inserted to the output from the control signal generating part 13 by an auxiliary signal superposing part 14, and the output is applied to a transformer T11. The output induced in the secondary side of the trabsformer T11 is switched by synchronizing switches S1 and S2 and is demodulated by synthesis. Since this demodulation output has the inserted auxiliary signal for cancelling DC offset, the integral output in a capacitor C3 is in the no-output state where no DC components remains at all.
COPYRIGHT: (C)1982,JPO&Japio
JP55174264A 1980-12-10 1980-12-10 Power amplifying device Pending JPS5797710A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55174264A JPS5797710A (en) 1980-12-10 1980-12-10 Power amplifying device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55174264A JPS5797710A (en) 1980-12-10 1980-12-10 Power amplifying device

Publications (1)

Publication Number Publication Date
JPS5797710A true JPS5797710A (en) 1982-06-17

Family

ID=15975593

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55174264A Pending JPS5797710A (en) 1980-12-10 1980-12-10 Power amplifying device

Country Status (1)

Country Link
JP (1) JPS5797710A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1994021036A1 (en) * 1993-03-02 1994-09-15 Kirn Larry J Switching amplifier with impedance transformation output stage
AU721511B2 (en) * 1996-12-11 2000-07-06 Gn Netcom A/S Class D amplifier

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1994021036A1 (en) * 1993-03-02 1994-09-15 Kirn Larry J Switching amplifier with impedance transformation output stage
AU721511B2 (en) * 1996-12-11 2000-07-06 Gn Netcom A/S Class D amplifier
US6191650B1 (en) 1996-12-11 2001-02-20 G/N Netcom A/S Class d amplifier with pulse width modulation and a very low power consumption

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