JPS5797467A - In-circuit testing method - Google Patents

In-circuit testing method

Info

Publication number
JPS5797467A
JPS5797467A JP55174095A JP17409580A JPS5797467A JP S5797467 A JPS5797467 A JP S5797467A JP 55174095 A JP55174095 A JP 55174095A JP 17409580 A JP17409580 A JP 17409580A JP S5797467 A JPS5797467 A JP S5797467A
Authority
JP
Japan
Prior art keywords
lead wires
connector
automatic
probers
printed board
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP55174095A
Other languages
Japanese (ja)
Inventor
Nobuhiko Kuribayashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP55174095A priority Critical patent/JPS5797467A/en
Publication of JPS5797467A publication Critical patent/JPS5797467A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2801—Testing of printed circuits, backplanes, motherboards, hybrid circuits or carriers for multichip packages [MCP]
    • G01R31/281—Specific types of tests or tests for a specific type of fault, e.g. thermal mapping, shorts testing

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Tests Of Electronic Circuits (AREA)

Abstract

PURPOSE:To adapt various printed boards by using a prober driving table which has automatic probers whose variable locations are selectively arranged against contact points on wiring as fittable free at the upper side of a printed board. CONSTITUTION:A prober driving table 11 provided with automatic probers 121- 123 whose contact points within prescribed ranges are varies in directions X and Y selectively is set freely over a printed board 1. The connector terminals of the printed board 1 are connected to a connector 15 and lead wires from the connector 15 are connected to a scanner to perform automatic scanning among those lead wires on the basis of a program in a CPU10. Then, impedance is measured among an optional number of points selected among lead wires 131-133 from the automatic probers 121-123 and the lead wires from the connector 15. The automatic probers 121-123 are positioned by a prober control part 14 according to the kinds of various printed boards 1.
JP55174095A 1980-12-10 1980-12-10 In-circuit testing method Pending JPS5797467A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55174095A JPS5797467A (en) 1980-12-10 1980-12-10 In-circuit testing method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55174095A JPS5797467A (en) 1980-12-10 1980-12-10 In-circuit testing method

Publications (1)

Publication Number Publication Date
JPS5797467A true JPS5797467A (en) 1982-06-17

Family

ID=15972559

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55174095A Pending JPS5797467A (en) 1980-12-10 1980-12-10 In-circuit testing method

Country Status (1)

Country Link
JP (1) JPS5797467A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2533403A1 (en) * 1982-09-17 1984-03-23 Orion Electronic Sarl Method for checking electrical circuits and equipment for implementing this method.

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2533403A1 (en) * 1982-09-17 1984-03-23 Orion Electronic Sarl Method for checking electrical circuits and equipment for implementing this method.

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