JPS5797239A - Time division multidimensional connector - Google Patents
Time division multidimensional connectorInfo
- Publication number
- JPS5797239A JPS5797239A JP17274280A JP17274280A JPS5797239A JP S5797239 A JPS5797239 A JP S5797239A JP 17274280 A JP17274280 A JP 17274280A JP 17274280 A JP17274280 A JP 17274280A JP S5797239 A JPS5797239 A JP S5797239A
- Authority
- JP
- Japan
- Prior art keywords
- signal
- information
- memory
- time slot
- speed
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B7/00—Radio transmission systems, i.e. using radiation field
- H04B7/14—Relay systems
- H04B7/15—Active relay systems
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Time-Division Multiplex Systems (AREA)
- Radio Relay Systems (AREA)
Abstract
PURPOSE:To achieve simultaneous communication with high utilizing efficiency, by assigning a time slot with lower speed than the transmission simultaneous information speed as a satellite line toward opposite direction used for the transmission of response information from the incoming terminal less in the amount of information substantially. CONSTITUTION:An extension buffer circuit 1 receives a burst signal (a) trasmitted from a transmission terminal via a satellite line at a time slot T and converts it into a simultaneous signal (b) and transmits it to an incoming terminal 2. The said incoming terminal 2 returns the response information to a synchronism detection circuit 3 as a signal (c) in the same speed as the transmitted information speed. This circuit 3 detects the response information only with a flag and transmits it to a memory 4 as a signal (d), and supplies the signal (e) from the memory 4 to a compression buffer 5. The buffer 5 converts a signal in the said memory 4 into a signal of one time slot in T1-TS designated at the set of line.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP17274280A JPS5797239A (en) | 1980-12-08 | 1980-12-08 | Time division multidimensional connector |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP17274280A JPS5797239A (en) | 1980-12-08 | 1980-12-08 | Time division multidimensional connector |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5797239A true JPS5797239A (en) | 1982-06-16 |
Family
ID=15947469
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP17274280A Pending JPS5797239A (en) | 1980-12-08 | 1980-12-08 | Time division multidimensional connector |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5797239A (en) |
-
1980
- 1980-12-08 JP JP17274280A patent/JPS5797239A/en active Pending
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