JPS5791485A - Electronic timepiece with pace regulator - Google Patents

Abstract

PURPOSE:To perform pace regulation of good accuracy with simple circuits by setting and resetting suitable stages of FFs of frequency dividing stages directly thereby regulating pace. CONSTITUTION:When a pace regulating signal P is inputted to a waveform shaping part 12, the output A of an advance and delay assigning FF13 is the H level in the case of advance correction and therefore it is not reset unless the Q output of an FF4 of the frequency dividing stage goes to the H level. On the other hand, when the Q' output of a frequency dividing stage 2 and the Q output of the stage before this go both to the H level through an AND gate 18 on account of the rising of the output signal P' of the part 12 to the H level, the FF3 is reset. When the Q' output of the stage 2 is the H level through an AND gate 17, the FF4 is reset. Next, when the Q output of the stage 2 falls, the FFs 3, 4 are triggered and the Q output of the FF4 goes to the H level. Namely, every time when the signal P is inputted, the Q output waveform of the FF4 is advanced by the prescribed period. On the other hand, in the case of delay correction, the Q output of the FF4 is delayed for a prescribed period at every inputting of the signal P.