JPS5782218A - Signal recording and reproducing system - Google Patents
Signal recording and reproducing systemInfo
- Publication number
- JPS5782218A JPS5782218A JP55158036A JP15803680A JPS5782218A JP S5782218 A JPS5782218 A JP S5782218A JP 55158036 A JP55158036 A JP 55158036A JP 15803680 A JP15803680 A JP 15803680A JP S5782218 A JPS5782218 A JP S5782218A
- Authority
- JP
- Japan
- Prior art keywords
- bits
- signal
- reproduction
- level
- outputted
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
- G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
- G11B20/10—Digital recording or reproducing
- G11B20/18—Error detection or correction; Testing, e.g. of drop-outs
- G11B20/1806—Pulse code modulation systems for audio signals
- G11B20/1813—Pulse code modulation systems for audio signals by adding special bits or symbols to the coded information
Landscapes
- Engineering & Computer Science (AREA)
- Multimedia (AREA)
- Signal Processing (AREA)
- Signal Processing For Digital Recording And Reproducing (AREA)
- Transmission Systems Not Characterized By The Medium Used For Transmission (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
Abstract
PURPOSE:To pick up clock information from a reproduction signal, by combining the clock information pickup technology when the level inverting interval of reproduction pulse waves is definite with the nature of a digital signal converted from an analog signal. CONSTITUTION:An input analog signal is AD-converted 1 into a digital signal in 16-bit. The level degradation circuit 2 makes code conversion indicating adjacent level that the least significant bit is zero and other bits are 1 when all the bits are 1, and the least significant bit 1 and other bits are 0 when all the bits are 0, and an error detection/correction code is added 3 and a synchronizing signal is added 4. A signal with level inversion is formed when the bits are 1 by a modulation circuit 5 and it is outputted to a recording head 7 via a recording amplifier 6. At reproduction, a synchronizing signal pattern is detected at a synchronizing signal separation circuit 13 after clock reproduction 11 and demodulation 12 and outputted through an error detection/correction 14.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP55158036A JPS5782218A (en) | 1980-11-10 | 1980-11-10 | Signal recording and reproducing system |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP55158036A JPS5782218A (en) | 1980-11-10 | 1980-11-10 | Signal recording and reproducing system |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5782218A true JPS5782218A (en) | 1982-05-22 |
Family
ID=15662866
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP55158036A Pending JPS5782218A (en) | 1980-11-10 | 1980-11-10 | Signal recording and reproducing system |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5782218A (en) |
-
1980
- 1980-11-10 JP JP55158036A patent/JPS5782218A/en active Pending
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