JPS5780886A - Television receiver - Google Patents

Television receiver

Info

Publication number
JPS5780886A
JPS5780886A JP55157484A JP15748480A JPS5780886A JP S5780886 A JPS5780886 A JP S5780886A JP 55157484 A JP55157484 A JP 55157484A JP 15748480 A JP15748480 A JP 15748480A JP S5780886 A JPS5780886 A JP S5780886A
Authority
JP
Japan
Prior art keywords
horizontal synchronizing
given
circuit
flicker
flop
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP55157484A
Other languages
Japanese (ja)
Other versions
JPS6157753B2 (en
Inventor
Fumio Maehara
Yukio Takada
Hirosuke Okano
Hiroaki Saeki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP55157484A priority Critical patent/JPS5780886A/en
Publication of JPS5780886A publication Critical patent/JPS5780886A/en
Publication of JPS6157753B2 publication Critical patent/JPS6157753B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N7/00—Television systems
    • H04N7/01—Conversion of standards, e.g. involving analogue television standards or digital television standards processed at pixel level
    • H04N7/0127—Conversion of standards, e.g. involving analogue television standards or digital television standards processed at pixel level by changing the field or frame frequency of the incoming video signal, e.g. frame rate converter
    • H04N7/0132—Conversion of standards, e.g. involving analogue television standards or digital television standards processed at pixel level by changing the field or frame frequency of the incoming video signal, e.g. frame rate converter the field or frame frequency of the incoming video signal being multiplied by a positive integer, e.g. for flicker reduction

Landscapes

  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Television Systems (AREA)

Abstract

PURPOSE:To eliminate the flicker on a display screen, by reading contents of a memory, where one-field components of information are stored, synchronously with a horizontal synchronizing signal where numbers N and M of scanning lines in odd and even fields satisfy equation N+M=525. CONSTITUTION:An input from a video detection output is given to an amplitude separating circuit 17, and synchronizing components are extracted and are given to a horizontal synchronizing separating circuit 19 and an integrating circuit 20. Horizontal synchronizing pulses from the horizontal synchronizing separating circuit 19 are given to a flip-flop 23. Meanwhile, the output of the integrating circuit 20 is given to a monostable multivibrator 22 through a waveform shaping circuit 21. Thus, a vertical synchronizing signal appears on a signal line 26. By using the horizontal synchronizing signal as a clock of the flip-flop 23 in this manner, the sum of numbers N and M of odd and even scanning lines is equal to 525, thus eliminating the flicker on the display screen.
JP55157484A 1980-11-07 1980-11-07 Television receiver Granted JPS5780886A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55157484A JPS5780886A (en) 1980-11-07 1980-11-07 Television receiver

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55157484A JPS5780886A (en) 1980-11-07 1980-11-07 Television receiver

Publications (2)

Publication Number Publication Date
JPS5780886A true JPS5780886A (en) 1982-05-20
JPS6157753B2 JPS6157753B2 (en) 1986-12-08

Family

ID=15650684

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55157484A Granted JPS5780886A (en) 1980-11-07 1980-11-07 Television receiver

Country Status (1)

Country Link
JP (1) JPS5780886A (en)

Also Published As

Publication number Publication date
JPS6157753B2 (en) 1986-12-08

Similar Documents

Publication Publication Date Title
KR840002791A (en) Television receiver
ES473933A2 (en) Television system for displaying and recording paths of motion
US4051532A (en) Auxiliary signal processing circuit for television receivers
SE8007147L (en) IMAGE DATA DISPLAY CHALLENGE TO REPLACE A MIXED IMAGE SIGNAL, LIKE AN INTERFOLIED TELEVISION IMAGE
TW347640B (en) Video display apparatus displaying plural images simultaneously on a screen
JPS5482931A (en) Display unit for cathode ray tube
JPS54112122A (en) Picture display unit
US4068262A (en) Auxiliary variable coordinate sonic display system
KR910005685A (en) Signal waveform display device
JPS54142935A (en) Picture display system
JPS5780886A (en) Television receiver
JPS5566181A (en) Double-screen display television picture receiver
SE8401626D0 (en) SYNCHRONIZATION INPUT FOR ALFANUMERIC PRESENTATION ON THE SCREEN OF A TELEVISION RECEIVER
FI894154A (en) SKENBART LINJELAOST SKRIVKLOCKA FOER BILD-I-BILD-VIDEOTILLAEMPNINGAR.
KR900006305Y1 (en) Horizontal and vertical synchronizing signal and field detecting circuit for video signal
JP3083031B2 (en) Teletext broadcasting device
KR920014287A (en) Control Function Synchronization Method and Device
JPS5713868A (en) Two-screen television receiver
JPS5753189A (en) Picture receiver for measurement
JPS554141A (en) Still picture receiver circuit
JPS5617583A (en) Television picture receiver
JPS5765070A (en) Television receiver
JPS5731280A (en) Simultaneous display television receiver of colored plural screens
JPS5648760A (en) Vertical synchronism detecting circuit
SU410572A1 (en)