JPS5779726A - Highly reliable logical circuit - Google Patents

Highly reliable logical circuit

Info

Publication number
JPS5779726A
JPS5779726A JP55155003A JP15500380A JPS5779726A JP S5779726 A JPS5779726 A JP S5779726A JP 55155003 A JP55155003 A JP 55155003A JP 15500380 A JP15500380 A JP 15500380A JP S5779726 A JPS5779726 A JP S5779726A
Authority
JP
Japan
Prior art keywords
counter
binary counter
logical circuit
oscillation
output signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP55155003A
Other languages
Japanese (ja)
Inventor
Shigehiro Funatsu
Masanobu Takahashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP55155003A priority Critical patent/JPS5779726A/en
Publication of JPS5779726A publication Critical patent/JPS5779726A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/027—Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
    • H03K3/037—Bistable circuits
    • H03K3/0375—Bistable circuits provided with means for increasing reliability; for protection; for ensuring a predetermined initial state when the supply voltage has been applied; for storing the actual state when the supply voltage fails

Landscapes

  • Logic Circuits (AREA)

Abstract

PURPOSE:To allow relief instantly by detecting oscillation failure of a logical circuit, by connecting a counter circuit provided with a reset function and an overflow detecting function to a feedback line of the logical circuit. CONSTITUTION:If an output signal 3 of a latch circuit consisting of NAND gates 11, 12 is in oscillating state due to failure, since the output signal 3 is applied to a binary counter 14 of n bits as a trigger signal, the content of the binary counter 14 is summed by one at every period of oscillation. When the binary counter 14 overflows, the production of the overflow state is reported with an output signal 8 and the production of oscillation to the latch circuit is known. The binary counter 14 clears the content of counter at an arbitrary point of time with a reset signal 7.
JP55155003A 1980-11-04 1980-11-04 Highly reliable logical circuit Pending JPS5779726A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55155003A JPS5779726A (en) 1980-11-04 1980-11-04 Highly reliable logical circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55155003A JPS5779726A (en) 1980-11-04 1980-11-04 Highly reliable logical circuit

Publications (1)

Publication Number Publication Date
JPS5779726A true JPS5779726A (en) 1982-05-19

Family

ID=15596567

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55155003A Pending JPS5779726A (en) 1980-11-04 1980-11-04 Highly reliable logical circuit

Country Status (1)

Country Link
JP (1) JPS5779726A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4849653A (en) * 1987-03-26 1989-07-18 Kabushiki Kaisha Toshiba Semiconductor circuit device for preventing an output of a bistable circuit from becoming unstable
JP2009186033A (en) * 2008-02-01 2009-08-20 Daikin Ind Ltd Two-stage compression type refrigerating device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4849653A (en) * 1987-03-26 1989-07-18 Kabushiki Kaisha Toshiba Semiconductor circuit device for preventing an output of a bistable circuit from becoming unstable
JP2009186033A (en) * 2008-02-01 2009-08-20 Daikin Ind Ltd Two-stage compression type refrigerating device

Similar Documents

Publication Publication Date Title
JPS5779726A (en) Highly reliable logical circuit
JPS5362908A (en) Bit clock reproducer
JPS5299031A (en) Three value input detecting circuit
JPS5542024A (en) Input circuit of electronic clock
JPS56117423A (en) Binary coding circuit by multistage threshold level
JPS57150221A (en) On and off detecting circuit of switch
JPS5370639A (en) 1-bit arithmetic operation circuit
JPS56161717A (en) Input signal protecting circuit
JPS5332663A (en) Numeric setting unit
JPS5375848A (en) Schmitt trigger circuit
JPS5539474A (en) Flip-flop circuit
JPS56106404A (en) Oscillating circuit
JPS56114435A (en) Electronic timer
JPS57109029A (en) Input system
JPS57103084A (en) Electronic circuit for timepiece
JPS6484343A (en) Interruption control circuit
JPS56108145A (en) Logical operation device
JPS56157121A (en) Latch circuit
JPS55162623A (en) Monostable multivibrator
JPS52137967A (en) Electronic counter
JPS5533383A (en) Counter circuit
JPS6413808A (en) Latching circuit
JPS57140055A (en) Cmi coding circuit
JPS5386268A (en) Digital timepiece
JPS5698940A (en) Frequency division circuit