JPS577649A - Error-correctable data transmitting method - Google Patents
Error-correctable data transmitting methodInfo
- Publication number
- JPS577649A JPS577649A JP8265680A JP8265680A JPS577649A JP S577649 A JPS577649 A JP S577649A JP 8265680 A JP8265680 A JP 8265680A JP 8265680 A JP8265680 A JP 8265680A JP S577649 A JPS577649 A JP S577649A
- Authority
- JP
- Japan
- Prior art keywords
- word
- error
- check
- parity
- interleaver
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
- H04L1/0056—Systems characterized by the type of code used
- H04L1/0071—Use of interleaving
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Error Detection And Correction (AREA)
Abstract
PURPOSE:To improve the performance of error correction by adding a one parity bit to each word each check word of PCM data to be transmitted. CONSTITUTION:At the output of a parity interleaver 1, PCM data series of 12 channels appear, and words in them are supplied to an encoder 2 one after another to form the 1st check words P12n and Q12n. Further, 12 PCM data series and two check word series are supplied to an interleaver 3. One word each in an output data series of this interleaver 3 is supplied to an encoder 4 to form the 2nd check words R12n and S12n, and a circuit 10 adds a parity bit to each word. This data is applied to the input of en error correcting decoder, and a checker 11 makes a word-by-word parity check. On the basis of a syndrome, a decoder 17 makes an error correction, and a decoder 19 generates an error syndrome by data included in the 1st error correction block and a parity check matrix, thereby correcting the error.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP8265680A JPS577649A (en) | 1980-06-17 | 1980-06-17 | Error-correctable data transmitting method |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP8265680A JPS577649A (en) | 1980-06-17 | 1980-06-17 | Error-correctable data transmitting method |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS577649A true JPS577649A (en) | 1982-01-14 |
Family
ID=13780470
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP8265680A Pending JPS577649A (en) | 1980-06-17 | 1980-06-17 | Error-correctable data transmitting method |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS577649A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS58131843A (en) * | 1982-01-21 | 1983-08-05 | エヌ・ベ−・フイリツプス・フル−イランペンフアブリケン | Error correcting method and device |
-
1980
- 1980-06-17 JP JP8265680A patent/JPS577649A/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS58131843A (en) * | 1982-01-21 | 1983-08-05 | エヌ・ベ−・フイリツプス・フル−イランペンフアブリケン | Error correcting method and device |
JPH0436487B2 (en) * | 1982-01-21 | 1992-06-16 | Fuiritsupusu Furuuiranpenfuaburiken Nv |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
ATE39776T1 (en) | ERROR CORRECTION METHOD FOR TRANSMISSION OF SUB-BLOCKS OF DATA, APPARATUS FOR CARRYING OUT THE METHOD, DECODERS FOR USE IN THIS METHOD, AND APPARATUS INCLUDING THIS DECODER. | |
JPS574629A (en) | Data transmitting method capable of correction of error | |
EP0426657A3 (en) | ||
JPS5556744A (en) | Pcm signal transmission device | |
EP0166269A3 (en) | Error correction for multiple bit output chips | |
CA2013158A1 (en) | Error correction method and apparatus | |
JPS6418860A (en) | Error dispersion for digital information and organization of error dispersion form | |
JPS55115753A (en) | Pcm signal transmission method | |
EP0092960A3 (en) | Apparatus for checking and correcting digital data | |
EP0310089A3 (en) | Data transmission method for interleaved data | |
EP0112676A3 (en) | Methods of and apparatus for correcting errors in binary data | |
EP0101218A3 (en) | Methods of correcting errors in binary data | |
JPS5724143A (en) | Error correcting method | |
JPS5710561A (en) | Error correcting method | |
ES534728A0 (en) | CODING, DECODING AND CORRECTIONS PROCEDURE FOR DIGITAL SIGNAL T ERRORS TRANSMITTED IN THE REED-SOLOMON CODE | |
JPS577649A (en) | Error-correctable data transmitting method | |
JPS57171860A (en) | Method for encoding error correction | |
JPS5637748A (en) | Coding method | |
WO1995023384A3 (en) | Error correctable data transmission method and device based on semi-cyclic codes | |
JPS55147052A (en) | Signal transmission system | |
JPS5713836A (en) | Channel synchronization system | |
JPS5765937A (en) | Split duplex interleave method | |
JPS57138237A (en) | Transmission system for error correction parallel data | |
JPS5725046A (en) | Cyclic redundancy check operating circuit | |
Means et al. | A backpropagation network error correcting decoder for convolutional and block codes. |