JPS5775048A - Data transmission device - Google Patents
Data transmission deviceInfo
- Publication number
- JPS5775048A JPS5775048A JP15115080A JP15115080A JPS5775048A JP S5775048 A JPS5775048 A JP S5775048A JP 15115080 A JP15115080 A JP 15115080A JP 15115080 A JP15115080 A JP 15115080A JP S5775048 A JPS5775048 A JP S5775048A
- Authority
- JP
- Japan
- Prior art keywords
- interruption
- data
- flag
- receiving
- received
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
- G06F13/24—Handling requests for interconnection or transfer for access to input/output bus using interrupt
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Small-Scale Networks (AREA)
- Computer And Data Communications (AREA)
Abstract
PURPOSE:To perform the backup processing of interruption data only in a master station, by not determining a destination of an interruption in a slave station and by giving a flag, which determines whether the interruption can be received or not, in the master station which receives it. CONSTITUTION:An input channel 11 of a CPU sets an interruption permitting flag in an address area corresponding to interruption data, which should be received, in an interruption permitting flag memory 15 when interruption data can be received, but the input channel 11 resets this flag when interruption data cannot be received. Meanwhile, when interruption data is inputted from a receiving line 81 to a transmission interface circuit 18, the circuit 18 sets a receiving flag in an address corresponding to interruption data in a receiving flag memory 16 and writes contents of received data in a receiving data memory 17. An interruption control circuit 14 scans the receiving flag memory 16 successively, and if the corresponding interruption permitting flag does not exist in the flag memory 15, the circuit 14 transfers receiving data of the receiving data memory 17 to another backup device from a transmission line 82 through the circuit 18.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP15115080A JPS5775048A (en) | 1980-10-28 | 1980-10-28 | Data transmission device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP15115080A JPS5775048A (en) | 1980-10-28 | 1980-10-28 | Data transmission device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5775048A true JPS5775048A (en) | 1982-05-11 |
Family
ID=15512449
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP15115080A Pending JPS5775048A (en) | 1980-10-28 | 1980-10-28 | Data transmission device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5775048A (en) |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5410601A (en) * | 1977-06-27 | 1979-01-26 | Hitachi Ltd | Representative address control system for loop communication system |
-
1980
- 1980-10-28 JP JP15115080A patent/JPS5775048A/en active Pending
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5410601A (en) * | 1977-06-27 | 1979-01-26 | Hitachi Ltd | Representative address control system for loop communication system |
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