JPS5773439A - Command chain system - Google Patents

Command chain system

Info

Publication number
JPS5773439A
JPS5773439A JP14930480A JP14930480A JPS5773439A JP S5773439 A JPS5773439 A JP S5773439A JP 14930480 A JP14930480 A JP 14930480A JP 14930480 A JP14930480 A JP 14930480A JP S5773439 A JPS5773439 A JP S5773439A
Authority
JP
Japan
Prior art keywords
command chain
command
input
output device
channel
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14930480A
Other languages
Japanese (ja)
Inventor
Tokihiko Tomota
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP14930480A priority Critical patent/JPS5773439A/en
Publication of JPS5773439A publication Critical patent/JPS5773439A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/10—Program control for peripheral devices
    • G06F13/12—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
    • G06F13/122—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware performs an I/O function other than control of data transfer

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)

Abstract

PURPOSE:To decrease the frequency of interruption and to realize a high-speed command chain, by installing a command chain flag holding means an input/output device number register and a command chain deciding means respectively within a channel. CONSTITUTION:An input/output device number register 4, a command chain flag holding means 5 and a command chain deciding means 6 are provided within a channel 2. When an input/output controller is started for the execution of the first chained command, a command chain indication signal is immediately delivered to an input/output device 3 if the means 6 shows the command chain. Then the input/ output device number read out from the register 4 is transmitted to the device 3 to apply the start for the next command. As a result, the frequency of interruption is decreased to a microprogram from channel to realize the high-speed execution of the command chain.
JP14930480A 1980-10-27 1980-10-27 Command chain system Pending JPS5773439A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14930480A JPS5773439A (en) 1980-10-27 1980-10-27 Command chain system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14930480A JPS5773439A (en) 1980-10-27 1980-10-27 Command chain system

Publications (1)

Publication Number Publication Date
JPS5773439A true JPS5773439A (en) 1982-05-08

Family

ID=15472214

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14930480A Pending JPS5773439A (en) 1980-10-27 1980-10-27 Command chain system

Country Status (1)

Country Link
JP (1) JPS5773439A (en)

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