JPS5771578A - Address translation selecting circuit for memory array - Google Patents

Address translation selecting circuit for memory array

Info

Publication number
JPS5771578A
JPS5771578A JP56129498A JP12949881A JPS5771578A JP S5771578 A JPS5771578 A JP S5771578A JP 56129498 A JP56129498 A JP 56129498A JP 12949881 A JP12949881 A JP 12949881A JP S5771578 A JPS5771578 A JP S5771578A
Authority
JP
Japan
Prior art keywords
memory array
address translation
selecting circuit
translation selecting
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP56129498A
Other languages
Japanese (ja)
Other versions
JPS5918790B2 (en
Inventor
Buudon Jieraaru
Doni Berunaaru
Do Guriberu Birujiinii
Morie Pieeru
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of JPS5771578A publication Critical patent/JPS5771578A/en
Publication of JPS5918790B2 publication Critical patent/JPS5918790B2/en
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
    • G11C17/14—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
    • G11C17/18—Auxiliary circuits, e.g. for writing into memory
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G11C11/414—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the bipolar type
    • G11C11/415—Address circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/08—Address circuits; Decoders; Word-line control circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Static Random-Access Memory (AREA)
JP56129498A 1980-09-26 1981-08-20 Address decoding selection circuit for memory array Expired JPS5918790B2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR804300192 1980-09-26
EP80430019A EP0048782B1 (en) 1980-09-26 1980-09-26 Decoding and selection circuit for monolithic memory

Publications (2)

Publication Number Publication Date
JPS5771578A true JPS5771578A (en) 1982-05-04
JPS5918790B2 JPS5918790B2 (en) 1984-04-28

Family

ID=8187423

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56129498A Expired JPS5918790B2 (en) 1980-09-26 1981-08-20 Address decoding selection circuit for memory array

Country Status (4)

Country Link
US (1) US4394752A (en)
EP (1) EP0048782B1 (en)
JP (1) JPS5918790B2 (en)
DE (1) DE3070584D1 (en)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4608672A (en) * 1983-07-14 1986-08-26 Honeywell Inc. Semiconductor memory
JPS6080195A (en) * 1983-10-07 1985-05-08 Fujitsu Ltd Semiconductor memory
EP0183885B1 (en) * 1984-11-30 1989-04-05 International Business Machines Corporation Memory using conventional cells to perform a ram or an associative memory function
FR2580420B1 (en) * 1985-04-16 1991-05-31 Radiotechnique Compelec DIODE DECODER, PARTICULARLY FOR USE IN A BIPOLAR MEMORY
US5276363A (en) * 1992-08-13 1994-01-04 International Business Machines Corporation Zero power decoder/driver
US5673218A (en) 1996-03-05 1997-09-30 Shepard; Daniel R. Dual-addressed rectifier storage device
US6956757B2 (en) * 2000-06-22 2005-10-18 Contour Semiconductor, Inc. Low cost high density rectifier matrix memory
US7593256B2 (en) * 2006-03-28 2009-09-22 Contour Semiconductor, Inc. Memory array with readout isolation
US7813157B2 (en) * 2007-10-29 2010-10-12 Contour Semiconductor, Inc. Non-linear conductor memory
US20090225621A1 (en) * 2008-03-05 2009-09-10 Shepard Daniel R Split decoder storage array and methods of forming the same
WO2009149061A2 (en) * 2008-06-02 2009-12-10 Contour Semiconductor, Inc. Diode decoder array with non-sequential layout and methods of forming the same
US8325556B2 (en) * 2008-10-07 2012-12-04 Contour Semiconductor, Inc. Sequencing decoder circuit

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4007451A (en) * 1975-05-30 1977-02-08 International Business Machines Corporation Method and circuit arrangement for operating a highly integrated monolithic information store
FR2443118A1 (en) * 1978-11-30 1980-06-27 Ibm France DEVICE FOR POWERING MONOLITHIC MEMORIES

Also Published As

Publication number Publication date
US4394752A (en) 1983-07-19
DE3070584D1 (en) 1985-06-05
EP0048782B1 (en) 1985-05-02
EP0048782A1 (en) 1982-04-07
JPS5918790B2 (en) 1984-04-28

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