JPS5769345A - Protection system of computer - Google Patents

Protection system of computer

Info

Publication number
JPS5769345A
JPS5769345A JP55142327A JP14232780A JPS5769345A JP S5769345 A JPS5769345 A JP S5769345A JP 55142327 A JP55142327 A JP 55142327A JP 14232780 A JP14232780 A JP 14232780A JP S5769345 A JPS5769345 A JP S5769345A
Authority
JP
Japan
Prior art keywords
computer
disaster
hardware
tier
board
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP55142327A
Other languages
Japanese (ja)
Other versions
JPS6059609B2 (en
Inventor
Haruhiko Yamamoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP55142327A priority Critical patent/JPS6059609B2/en
Publication of JPS5769345A publication Critical patent/JPS5769345A/en
Publication of JPS6059609B2 publication Critical patent/JPS6059609B2/en
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring

Abstract

PURPOSE:To perfectly protect a computer from a disaster or an abnormal environment, by constituting the connection of the computer with plural tiers and installing a tier to each timer excepting the highest tier to deliver an abnormal information signal to each tier. CONSTITUTION:The signal supplied from an operating system 2 is supplied to a timer function of a disaster preventing control monitor board 9 via a hardware 13 of a computer. A facilities 14 comprising an air conditioning facilities, an electric power facilities, etc. is connected to the baord 9. At the same time, a disaster preventing environment sensor 12 is connected to the board 9. When the board 9 detects a disaster or an abnormal environment with the signal applied from the sensor 12, the time t1 is set at the timer function and sent to the hardware 13. Then the time t2 is set at the hardware 13. At the same time, the occurrence of a fault is informed to the system 2, and accordingly the contents of the fault is logged out or various types of shunting processes are carried out in the system 2. Thus a computer is perfectly proteced from a disaster or an abnormal environment.
JP55142327A 1980-10-12 1980-10-12 Computer protection methods Expired JPS6059609B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55142327A JPS6059609B2 (en) 1980-10-12 1980-10-12 Computer protection methods

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55142327A JPS6059609B2 (en) 1980-10-12 1980-10-12 Computer protection methods

Publications (2)

Publication Number Publication Date
JPS5769345A true JPS5769345A (en) 1982-04-28
JPS6059609B2 JPS6059609B2 (en) 1985-12-26

Family

ID=15312760

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55142327A Expired JPS6059609B2 (en) 1980-10-12 1980-10-12 Computer protection methods

Country Status (1)

Country Link
JP (1) JPS6059609B2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111899486A (en) * 2020-08-17 2020-11-06 航天新长征大道科技有限公司 Logistics center safety monitoring method, device, equipment and storage medium

Also Published As

Publication number Publication date
JPS6059609B2 (en) 1985-12-26

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