JPS5769326A - Digital control system - Google Patents
Digital control systemInfo
- Publication number
- JPS5769326A JPS5769326A JP55142069A JP14206980A JPS5769326A JP S5769326 A JPS5769326 A JP S5769326A JP 55142069 A JP55142069 A JP 55142069A JP 14206980 A JP14206980 A JP 14206980A JP S5769326 A JPS5769326 A JP S5769326A
- Authority
- JP
- Japan
- Prior art keywords
- control
- processors
- control cycle
- cycle
- timing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B5/00—Anti-hunting arrangements
- G05B5/01—Anti-hunting arrangements electric
Landscapes
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Automation & Control Theory (AREA)
- Feedback Control In General (AREA)
Abstract
PURPOSE:To compensate the effect due to the fluctation of control cycle caused by an external function and to maintain the stability of control, by measuring the control cycle given from a timing device and giving the automatic control to the control constant of a control subject in accordance with the measured control cycle. CONSTITUTION:Control subjects 9-11 are provided corresponding to processors 2-4, respectively, and the processors 2-4 control periodically the subjects 9-11, respectively by a timing command 12 given from a timing system 1. Timing devices 5-7 are connected to the processors 2-4, respectively, and a real time condition signal 15 is supplied to the system 1 from the processors 2-4. Each of these processors fetches the commmand 12 from the system 12 in the form of an interruption signal and calculates the control gain during the control cycle by using the count value of a timer as a measurement control cycle to secure the automatic change of the control gain of the control cycle. Then the adjustment is secured for a control subject 8 by the system 1 to maintain the stability of control.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP55142069A JPS5769326A (en) | 1980-10-13 | 1980-10-13 | Digital control system |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP55142069A JPS5769326A (en) | 1980-10-13 | 1980-10-13 | Digital control system |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5769326A true JPS5769326A (en) | 1982-04-28 |
Family
ID=15306699
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP55142069A Pending JPS5769326A (en) | 1980-10-13 | 1980-10-13 | Digital control system |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5769326A (en) |
-
1980
- 1980-10-13 JP JP55142069A patent/JPS5769326A/en active Pending
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