JPS5768677A - Converter - Google Patents

Converter

Info

Publication number
JPS5768677A
JPS5768677A JP55144421A JP14442180A JPS5768677A JP S5768677 A JPS5768677 A JP S5768677A JP 55144421 A JP55144421 A JP 55144421A JP 14442180 A JP14442180 A JP 14442180A JP S5768677 A JPS5768677 A JP S5768677A
Authority
JP
Japan
Prior art keywords
frequency
clock signals
converter
signals
saturation
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP55144421A
Other languages
Japanese (ja)
Inventor
Kiyoto Sudo
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
TDK Corp
Original Assignee
TDK Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by TDK Corp filed Critical TDK Corp
Priority to JP55144421A priority Critical patent/JPS5768677A/en
Publication of JPS5768677A publication Critical patent/JPS5768677A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
    • H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
    • H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M7/53—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M7/537—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters
    • H02M7/538—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters in a push-pull configuration
    • H02M7/5381—Parallel type

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Dc-Dc Converters (AREA)
  • Inverter Devices (AREA)

Abstract

PURPOSE:To stabilize and control the oscillation frequency of the converter by stabilizing the frequency of the clock signals of a clock signal generating circuit to a high degree. CONSTITUTION:The clock signals of the clock signal generating circuit 25 are amplified by means of a transistor 20, and currents corresponding to the clock signals flow through control winding 10C, 10D. Consequently, an oscillation transformer 10 repeats saturation periodically, and the interruption and conduction of transistors 1A, 1B are changed over at every saturation. This is, when the frequency of the clock signals is 2f, the converter shynchronizes with the signals are oscillates frequency f. Accordingly, when the frequency of the clock signals is stabilized to a high degree, the oscillation frequency of the converter can be stabilized and controlled.
JP55144421A 1980-10-17 1980-10-17 Converter Pending JPS5768677A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55144421A JPS5768677A (en) 1980-10-17 1980-10-17 Converter

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55144421A JPS5768677A (en) 1980-10-17 1980-10-17 Converter

Publications (1)

Publication Number Publication Date
JPS5768677A true JPS5768677A (en) 1982-04-27

Family

ID=15361781

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55144421A Pending JPS5768677A (en) 1980-10-17 1980-10-17 Converter

Country Status (1)

Country Link
JP (1) JPS5768677A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62213581A (en) * 1986-03-12 1987-09-19 Kosuke Harada Power unit with core and fet

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4873725A (en) * 1972-01-10 1973-10-04

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4873725A (en) * 1972-01-10 1973-10-04

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62213581A (en) * 1986-03-12 1987-09-19 Kosuke Harada Power unit with core and fet

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