JPS5765969A - Signal processing device - Google Patents
Signal processing deviceInfo
- Publication number
- JPS5765969A JPS5765969A JP14349080A JP14349080A JPS5765969A JP S5765969 A JPS5765969 A JP S5765969A JP 14349080 A JP14349080 A JP 14349080A JP 14349080 A JP14349080 A JP 14349080A JP S5765969 A JPS5765969 A JP S5765969A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- slice
- bias
- output
- sample hold
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N7/00—Television systems
- H04N7/025—Systems for the transmission of digital non-picture data, e.g. of text during the active part of a television frame
- H04N7/035—Circuits for the digital non-picture data signal, e.g. for slicing of the data signal, for regeneration of the data-clock signal, for error detection or correction of the data signal
Landscapes
- Engineering & Computer Science (AREA)
- Multimedia (AREA)
- Signal Processing (AREA)
Abstract
PURPOSE:To shape a waveform accurately independently of the amplitude difference among plural signals added in plural horizontal scanning times during the vertical blanking interval, by providing a bias generating circuit which applies an optimum bias voltage to a binary signal slice circuit. CONSTITUTION:A slice bias adjusting circuit 23 detects the white level and the black level in the output of a detecting circuit 1 by detecting circuits 84 and 85 respectively, and an approximately average value of both levels is formed as a slice bias by a slice bias generating circuit 86. The output of the slice bias generating circuit 86 is smaple-held by a sample hold circuit 87. The output of a gate 70 is inputted to the sample hold circuit 87 to hold a DC bias corresponding to a constant waveform between a clock line signal CRI and a framing signal FC in the sample hold circuit 87. This output is used as the comparison reference voltage of a slice circuit 4 to receive desired information accurately between binary information different in amplitude.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP14349080A JPS5765969A (en) | 1980-10-13 | 1980-10-13 | Signal processing device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP14349080A JPS5765969A (en) | 1980-10-13 | 1980-10-13 | Signal processing device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5765969A true JPS5765969A (en) | 1982-04-21 |
JPS625505B2 JPS625505B2 (en) | 1987-02-05 |
Family
ID=15339913
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP14349080A Granted JPS5765969A (en) | 1980-10-13 | 1980-10-13 | Signal processing device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5765969A (en) |
-
1980
- 1980-10-13 JP JP14349080A patent/JPS5765969A/en active Granted
Also Published As
Publication number | Publication date |
---|---|
JPS625505B2 (en) | 1987-02-05 |
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