JPS5764931A - Automatic aligning method - Google Patents

Automatic aligning method

Info

Publication number
JPS5764931A
JPS5764931A JP55140612A JP14061280A JPS5764931A JP S5764931 A JPS5764931 A JP S5764931A JP 55140612 A JP55140612 A JP 55140612A JP 14061280 A JP14061280 A JP 14061280A JP S5764931 A JPS5764931 A JP S5764931A
Authority
JP
Japan
Prior art keywords
parallel lines
interval
lines
wafer
mask
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP55140612A
Other languages
Japanese (ja)
Inventor
Minoru Ikeda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP55140612A priority Critical patent/JPS5764931A/en
Publication of JPS5764931A publication Critical patent/JPS5764931A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)

Abstract

PURPOSE:To shorten the time of an automatic aligning method by providing a positioning target made of a plurality of parallel lines at a mask and a wafer and setting the interval of the parallel lines for the mask and the wafer to non-integer times, thereby enabling the detection of the relative position by one time optical scanning. CONSTITUTION:A target for a mask is, for example, formed of parallel lines 1, 2 perpendicularly crossed with parallel lines 1', 2' at an interval A, and a target for a wafer is formed of parallel lines 4, 5 perpendicularly crossed with parallel lines 4', 5' at an interval E. To align with both targets superposed, a light is scanned perpendicularly, for example, to the four parallel lines 1, 2, 4, 5, and photoelectric signals 1a-5a corresponding to the respective line positions are detected. The interval E is, for example, set to 2.5times the A, where there is a relationship of A<Enot equal to 2A or E<Anot equal to 2E. The relative position can be detected by one scanning even when two lines are superposed or three lines are arranged at the same interval, thereby eliminating the rescanning.
JP55140612A 1980-10-09 1980-10-09 Automatic aligning method Pending JPS5764931A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55140612A JPS5764931A (en) 1980-10-09 1980-10-09 Automatic aligning method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55140612A JPS5764931A (en) 1980-10-09 1980-10-09 Automatic aligning method

Publications (1)

Publication Number Publication Date
JPS5764931A true JPS5764931A (en) 1982-04-20

Family

ID=15272749

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55140612A Pending JPS5764931A (en) 1980-10-09 1980-10-09 Automatic aligning method

Country Status (1)

Country Link
JP (1) JPS5764931A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02301121A (en) * 1989-05-16 1990-12-13 Oki Electric Ind Co Ltd Alignment mark

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02301121A (en) * 1989-05-16 1990-12-13 Oki Electric Ind Co Ltd Alignment mark

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