JPS5761853U - - Google Patents
Info
- Publication number
- JPS5761853U JPS5761853U JP1980138794U JP13879480U JPS5761853U JP S5761853 U JPS5761853 U JP S5761853U JP 1980138794 U JP1980138794 U JP 1980138794U JP 13879480 U JP13879480 U JP 13879480U JP S5761853 U JPS5761853 U JP S5761853U
- Authority
- JP
- Japan
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
Landscapes
- Electric Clocks (AREA)
- Electric Connection Of Electric Components To Printed Circuits (AREA)
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
- Wire Bonding (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1980138794U JPS615804Y2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) | 1980-09-30 | 1980-09-30 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1980138794U JPS615804Y2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) | 1980-09-30 | 1980-09-30 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5761853U true JPS5761853U (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) | 1982-04-13 |
| JPS615804Y2 JPS615804Y2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) | 1986-02-21 |
Family
ID=29498789
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1980138794U Expired JPS615804Y2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) | 1980-09-30 | 1980-09-30 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS615804Y2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5945929U (ja) * | 1982-09-20 | 1984-03-27 | 富士電機株式会社 | 半導体素子の実装構造 |
| WO2007105763A1 (ja) * | 2006-03-14 | 2007-09-20 | Sharp Kabushiki Kaisha | 回路基板、電子回路装置及び表示装置 |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4860873A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) * | 1971-11-30 | 1973-08-25 | ||
| JPS4924076A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) * | 1972-05-05 | 1974-03-04 |
-
1980
- 1980-09-30 JP JP1980138794U patent/JPS615804Y2/ja not_active Expired
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4860873A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) * | 1971-11-30 | 1973-08-25 | ||
| JPS4924076A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) * | 1972-05-05 | 1974-03-04 |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5945929U (ja) * | 1982-09-20 | 1984-03-27 | 富士電機株式会社 | 半導体素子の実装構造 |
| WO2007105763A1 (ja) * | 2006-03-14 | 2007-09-20 | Sharp Kabushiki Kaisha | 回路基板、電子回路装置及び表示装置 |
| EP2007180A4 (en) * | 2006-03-14 | 2011-03-23 | Sharp Kk | PCB, ELECTRONIC CIRCUIT ARRANGEMENT AND DISPLAY |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS615804Y2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) | 1986-02-21 |